Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.
Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.
Signed-off-by: Dirk Behme <dirk.be...@de.bosch.com>
CC: Jason Chen <b02...@freescale.com>
CC: Jason Liu <r64...@freescale.com>
CC: Ranjani Vaidyanathan <ra5...@freescale.com>
CC: Stefano Babic <sba...@denx.de>
CC: Fabio Estevam <feste...@gmail.com>
---
arch/arm/cpu/armv7/mx6/soc.c | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 543b2cc..957ea34 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -77,10 +77,26 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr4);
}
+static void init_anatop_reg(void)
+{
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg = readl(&anatop->reg_core);
+
+ /*
+ * Increase the VDDSOC to 1.2V
+ * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
+ * and set them to 1.2V (0.7V + 0x14 * 0.025V)
+ */
+ reg = (reg & ~(0x1F << 18)) | (0x14 << 18);
+ writel(reg, &anatop->reg_core);
+}
+
int arch_cpu_init(void)
{
init_aips();
+ init_anatop_reg();
+
return 0;
}
#endif
--
1.7.0.4
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