On 2 April 2012 11:22, Donghwa Lee <dh09....@samsung.com> wrote:
> This patch is for EXYNOS Display driver.
>
>
> Signed-off-by: Donghwa Lee <dh09....@samsung.com>
> Signed-off-by: Inki Dae <inki....@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.p...@samsung.com>
> ---
> arch/arm/include/asm/arch-exynos/fb.h | 446
> +++++++++++++++++++++++++++++++++
> drivers/video/Makefile | 1 +
> drivers/video/exynos_fb.c | 219 ++++++++++++++++
> drivers/video/exynos_fb.h | 51 ++++
> drivers/video/exynos_fimd.c | 357 ++++++++++++++++++++++++++
> 5 files changed, 1074 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-exynos/fb.h
> create mode 100644 drivers/video/exynos_fb.c
> create mode 100644 drivers/video/exynos_fb.h
> create mode 100644 drivers/video/exynos_fimd.c
>
> diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
> new file mode 100644
> index 0000000..43210dc
> --- /dev/null
> +++ b/drivers/video/exynos_fb.c
> @@ -0,0 +1,219 @@
> +void lcd_ctrl_init(void *lcdbase)
> +{
> +
dead space
> + set_system_display_ctrl();
> + set_lcd_clk();
> +
> + /* initialize parameters which is specific to panel. */
> + init_panel_info(&panel_info);
> +
> + panel_width = panel_info.vl_width;
> + panel_height = panel_info.vl_height;
> +
> + exynos_lcd_init_mem(lcdbase, &panel_info);
> +
> + memset(lcdbase, 0, panel_width * panel_height * (32 >> 3));
> +
> + draw_samsung_logo(lcdbase);
> +
> + exynos_lcd_init(&panel_info);
> +}
> +
> +void lcd_enable(void)
> +{
> + lcd_panel_on(&panel_info);
> +}
> +
> +ulong calc_fbsize(void)
> +{
> + return exynos_fimd_calc_fbsize();
> +}
> +
> +/* dummy function */
> +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
> +{
> + return;
> +}
> +
> diff --git a/drivers/video/exynos_fb.h b/drivers/video/exynos_fb.h
> new file mode 100644
> index 0000000..e513f7a
> --- /dev/null
> +++ b/drivers/video/exynos_fb.h
> @@ -0,0 +1,51 @@
> +/*
> + * drivers/video/exynos_fb.h
> + *
> + * Copyright (C) 2012 Donghwa Lee <dh09....@samsung.com>
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. See the file COPYING in the main directory of this archive for
> + * more details.
> + *
> + * EXYNOS Frame Buffer Driver
> + * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
> + */
> +
> +#ifndef _EXYNOS_FB_H_
> +#define _EXYNOS_FB_H_
> +
> +#define MAX_CLOCK (86 * 1000000)
> +
> +enum exynos_fb_rgb_mode_t {
> + MODE_RGB_P = 0,
> + MODE_BGR_P = 1,
> + MODE_RGB_S = 2,
> + MODE_BGR_S = 3,
> +};
> +
> +enum exynos_cpu_auto_cmd_rate {
> + DISABLE_AUTO_FRM,
> + PER_TWO_FRM,
> + PER_FOUR_FRM,
> + PER_SIX_FRM,
> + PER_EIGHT_FRM,
> + PER_TEN_FRM,
> + PER_TWELVE_FRM,
> + PER_FOURTEEN_FRM,
> + PER_SIXTEEN_FRM,
> + PER_EIGHTEEN_FRM,
> + PER_TWENTY_FRM,
> + PER_TWENTY_TWO_FRM,
> + PER_TWENTY_FOUR_FRM,
> + PER_TWENTY_SIX_FRM,
> + PER_TWENTY_EIGHT_FRM,
> + PER_THIRTY_FRM,
> +};
> +
> +void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long
> fb_size,
> + unsigned long palette_size);
> +void exynos_fimd_lcd_init(vidinfo_t *vid);
> +unsigned long exynos_fimd_calc_fbsize(void);
> +
> +#endif
> +
dead space.
> diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
> new file mode 100644
> index 0000000..cfe5940
> --- /dev/null
> +++ b/drivers/video/exynos_fimd.c
> @@ -0,0 +1,357 @@
> +/*
> + * exynos LCD Controller Specific driver.
> + *
> + * Author: InKi Dae <inki....@samsung.com>
> + * Author: Donghwa Lee <dh09....@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <stdarg.h>
> +#include <linux/types.h>
> +#include <asm/io.h>
> +#include <lcd.h>
> +#include <div64.h>
> +
> +#include <asm/arch/clk.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/fb.h>
> +#include <asm/arch/gpio.h>
> +#include "exynos_fb.h"
> +
> +static unsigned long *lcd_base_addr;
> +static vidinfo_t *pvid;
> +
> +void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
> + u_long palette_size)
> +{
> + lcd_base_addr = (unsigned long *)screen_base;
> +
> + return;
no need return.
> +}
> +
> +static void exynos_fimd_set_dualrgb(unsigned int enabled)
> +{
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> + unsigned int cfg = 0;
> +
> + if (enabled) {
> + cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
> + EXYNOS_DUALRGB_VDEN_EN_ENABLE;
> +
> + /* in case of Line Split mode, MAIN_CNT doesn't neet to set.
> */
> + cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
> + EXYNOS_DUALRGB_MAIN_CNT(0);
> + }
> +
> + writel(cfg, &fimd_ctrl->dualrgb);
> +}
> +
> +static void exynos_fimd_set_par(unsigned int win_id)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> + unsigned long temp = win_id * 4;
> +
> + /* set window control */
> + cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
> EXYNOS_WINCON(win_id));
> +
> + cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
> + EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
> + EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
> + EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
> +
> + /* DATAPATH is DMA */
> + cfg |= EXYNOS_WINCON_DATAPATH_DMA;
> +
> + /* bpp is 32 */
> + cfg |= EXYNOS_WINCON_WSWP_ENABLE;
> +
> + /* dma burst is 16 */
> + cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
> +
> + /* pixel format is unpacked RGB888 */
> + cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
> +
> + writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
> EXYNOS_WINCON(win_id));
> +
> + /* set window position to x=0, y=0*/
> + cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
> + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
> EXYNOS_VIDOSD(win_id));
> +
> + cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
> + EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
> + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
> EXYNOS_VIDOSD(win_id));
> +
> + /* set window size for window0*/
> + cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
> + writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
> EXYNOS_VIDOSD(win_id));
> +}
> +
> +static void exynos_fimd_set_buffer_address(unsigned int win_id)
> +{
> + unsigned long start_addr, end_addr;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + start_addr = (unsigned long)lcd_base_addr;
> + end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
> + * pvid->vl_row);
> +
> + writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
> + EXYNOS_BUFFER_OFFSET(win_id));
> + writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
> + EXYNOS_BUFFER_OFFSET(win_id));
> +}
> +
> +static void exynos_fimd_set_clock(vidinfo_t *pvid)
> +{
> + unsigned int cfg = 0, div = 0, remainder, remainder_div;
> + unsigned long pixel_clock, src_clock;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> + u64 div64;
> +
> + if (get_pll_clk == NULL) {
> + printf("get_pll_clk is null.\n");
> + return;
> + }
> +
> + if (pvid->dual_lcd_enabled)
need brace.
> + pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
> + pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
> + pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
> + else if (pvid->interface_mode == FIMD_CPU_INTERFACE)
need brace.
> + pixel_clock = pvid->vl_freq * pvid->vl_width *
> pvid->vl_height *
> + (pvid->cs_setup + pvid->wr_setup + pvid->wr_act +
> + pvid->wr_hold + 1);
> + else
need brace.
> + pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
> + pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
> + pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
> +
> + src_clock = get_lcd_clk();
> +
> + cfg = readl(&fimd_ctrl->vidcon0);
> + cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
> + EXYNOS_VIDCON0_CLKVAL_F(0xFF) |
> + EXYNOS_VIDCON0_VCLKEN_MASK | EXYNOS_VIDCON0_CLKDIR_MASK);
> + cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
> + EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
> +
> + if (pixel_clock > MAX_CLOCK)
> + pixel_clock = MAX_CLOCK;
> +
> + div64 = (u64)get_lcd_clk();
> +
> + /* get quotient and remainder. */
> + remainder = do_div(div64, pixel_clock);
> + div = (u32) div64;
> +
> + remainder *= 10;
> + remainder_div = remainder / pixel_clock;
> +
> + /* round about one places of decimals. */
> + if (remainder_div >= 5)
> + div++;
> +
> + /* in case of dual lcd mode. */
> + if (pvid->dual_lcd_enabled)
> + div--;
> +
> + cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
> + writel(cfg, &fimd_ctrl->vidcon0);
> +}
> +
> +void exynos_set_trigger(void)
> +
dead space
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + cfg = readl(&fimd_ctrl->trigcon);
> +
> + cfg |= EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG;
> +
> + writel(cfg, &fimd_ctrl->trigcon);
> +}
> +
Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net
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