Since commit 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031
(net: fec_mxc: allow use with cache enabled) the FEC_MXC
driver uses flush_dcache_range() and invalidate_dcache_range()
functions. This driver is also configured for ARM1136 based
'flea3' and 'mx35pdk' boards which currently do not build
as there are no ARM1136 specific flush_dcache_range() and
invalidate_dcache_range() functions. Add various ARM1136
cache functions to fix building for 'flea3' and 'mx35pdk'.
Signed-off-by: Anatolij Gustschin <ag...@denx.de>
Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <fabio.este...@freescale.com>
---
This patch is completely untested, I have not the HW to test on.
Could someone test this patch? The mentioned commit to the
FEC_MXC driver is in u-boot-arm.git master.
Thanks,
Anatolij
arch/arm/cpu/arm1136/cpu.c | 78 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 78 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c
index 2b91631..43b4f5f 100644
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -75,3 +75,81 @@ static void cache_flush(void)
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches
and flush btb */
asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync
things */
}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+void invalidate_dcache_all(void)
+{
+ asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+}
+
+void flush_dcache_all(void)
+{
+ asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+ asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+static inline int bad_cache_range(unsigned long start, unsigned long stop)
+{
+ if ((start | stop) & (CONFIG_SYS_CACHELINE_SIZE - 1)) {
+ printf("Misaligned cache operation [%08lx, %08lx]\n",
+ start, stop);
+ return 1;
+ }
+
+ return 0;
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (bad_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ if (bad_cache_range(start, stop))
+ return;
+
+ while (start < stop) {
+ asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+ start += CONFIG_SYS_CACHELINE_SIZE;
+ }
+
+ asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+ flush_dcache_range(start, start + size);
+}
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+void invalidate_dcache_all(void)
+{
+}
+
+void flush_dcache_all(void)
+{
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
--
1.7.7.6
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