Donghwa,
On 30 March 2012 10:59, Donghwa Lee <dh09....@samsung.com> wrote:
> This patch is for EXYNOS Display driver.
>
> Signed-off-by: Donghwa Lee <dh09....@samsung.com>
> Signed-off-by: Inki Dae <inki....@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.p...@samsung.com>
> ---
> drivers/video/exynos_fb.c | 160 +++++++++++++++++
> drivers/video/exynos_fb.h | 62 +++++++
> drivers/video/exynos_fimd.c | 416
> +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 638 insertions(+), 0 deletions(-)
> create mode 100644 drivers/video/exynos_fb.c
> create mode 100644 drivers/video/exynos_fb.h
> create mode 100644 drivers/video/exynos_fimd.c
>
> diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
> new file mode 100644
> index 0000000..5067b22
> --- /dev/null
> +++ b/drivers/video/exynos_fb.c
> +static void lcd_clk_set(void)
> +{
> + struct exynos4_clock *clk =
> + (struct exynos4_clock *)samsung_get_base_clock();
> + struct exynos4_sysreg *sysreg =
> + (struct exynos4_sysreg *)samsung_get_base_sysreg();
> + unsigned int cfg = 0;
This function should be moved to exynos clock driver.
> +
> + /* system register path set */
> + cfg = readl(&sysreg->display_ctrl);
> + cfg |= (1 << 1);
> + writel(cfg, &sysreg->display_ctrl);
> +
> + /* set lcd src clock */
> + cfg &= ~(0xf);
> + cfg |= 0x6;
> + writel(cfg, &clk->src_lcd0);
> +
> + cfg = readl(&clk->gate_ip_lcd0);
> + cfg |= 1 << 0;
> + writel(cfg, &clk->gate_ip_lcd0);
> +
> + /* set fimd ratio */
> + cfg &= ~(0xf);
> + cfg |= 0x1;
> + writel(cfg, &clk->div_lcd0);
> +
> +}
> +
> +void lcd_ctrl_init(void *lcdbase)
> +{
> + lcd_clk_set();
> + /* initialize parameters which is specific to panel. */
> + init_panel_info(&panel_info);
> +
> + panel_width = panel_info.vl_width;
> + panel_height = panel_info.vl_height;
> +
> + exynos_lcd_init_mem(lcdbase, &panel_info);
> +
> + exynos_lcd_init(&panel_info);
> +}
> +
> +
> +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blud)
Maybe 'blud' is typo of 'blue'?
> +{
> + return;
Why you declared empty function?
> +}
> +
> +void lcd_enable(void)
> +{
> + lcd_panel_on(&panel_info);
> +}
> +
> +ulong calc_fbsize(void)
> +{
> + return exynos_fimd_calc_fbsize();
> +}
> diff --git a/drivers/video/exynos_fb.h b/drivers/video/exynos_fb.h
> new file mode 100644
> index 0000000..3b8b0f6
> --- /dev/null
> +++ b/drivers/video/exynos_fb.h
> @@ -0,0 +1,62 @@
> +/*
> + * drivers/video/exynos_fb.h
> + *
> + * Copyright (C) 2012 Donghwa Lee <dh09....@samsung.com>
> + *
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License. See the file COPYING in the main directory of this archive for
> + * more details.
> + *
> + * EXYNOS Frame Buffer Driver
> + * based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
> + */
> +
> +#ifndef _EXYNOS_FB_H_
> +#define _EXYNOS_FB_H_
> +
> +#define ON 1
> +#define OFF 0
> +
> +#define DEBUG
> +#undef DEBUG
> +#ifdef DEBUG
> +#define udebug(args...) printf(args)
> +#else
> +#define udebug(args...) do { } while (0)
> +#endif
Please don't make private debug macros.
Please use debug macro.
> +
> +enum exynos_fb_rgb_mode_t {
> + MODE_RGB_P = 0,
> + MODE_BGR_P = 1,
> + MODE_RGB_S = 2,
> + MODE_BGR_S = 3,
> +};
> +
> +enum s3cfb_cpu_auto_cmd_rate {
s3c? exynos?
Please make it clearly.
> + DISABLE_AUTO_FRM,
> + PER_TWO_FRM,
> + PER_FOUR_FRM,
> + PER_SIX_FRM,
> + PER_EIGHT_FRM,
> + PER_TEN_FRM,
> + PER_TWELVE_FRM,
> + PER_FOURTEEN_FRM,
> + PER_SIXTEEN_FRM,
> + PER_EIGHTEEN_FRM,
> + PER_TWENTY_FRM,
> + PER_TWENTY_TWO_FRM,
> + PER_TWENTY_FOUR_FRM,
> + PER_TWENTY_SIX_FRM,
> + PER_TWENTY_EIGHT_FRM,
> + PER_THIRTY_FRM,
> +};
> +
> +void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long
> fb_size,
> + unsigned long palette_size);
> +void exynos_fimd_lcd_init(vidinfo_t *vid);
> +unsigned long exynos_fimd_calc_fbsize(void);
> +void exynos_c100_gpio_setup(void);
> +void exynos_c110_gpio_setup(void);
Is it use somewhere?
> +
> +#endif
> +
> diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
> new file mode 100644
> index 0000000..4822741
> --- /dev/null
> +++ b/drivers/video/exynos_fimd.c
> @@ -0,0 +1,416 @@
> +/*
> + * exynos LCD Controller Specific driver.
> + *
> + * Author: InKi Dae <inki....@samsung.com>
> + * Author: Donghwa Lee <dh09....@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <stdarg.h>
> +#include <linux/types.h>
> +#include <asm/io.h>
> +#include <lcd.h>
> +#include <div64.h>
> +
> +#include <asm/arch/clk.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/fb.h>
> +#include <asm/arch/gpio.h>
> +#include "exynos_fb.h"
> +
> +static unsigned long *lcd_base_addr;
> +static vidinfo_t *pvid;
> +
> +void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
> + u_long palette_size)
> +{
> + lcd_base_addr = (unsigned long *)screen_base;
> +
> + udebug("lcd_base_addr(framebuffer memory) = %x\n", lcd_base_addr);
> +
> + return;
> +}
> +
> +static void exynos_fimd_set_dualrgb(unsigned int enabled)
> +{
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> + unsigned int cfg = 0;
> +
> + if (enabled) {
> + cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
> + EXYNOS_DUALRGB_VDEN_EN_ENABLE;
> +
> + /* in case of Line Split mode, MAIN_CNT doesn't neet to set.
> */
> + cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col/2) |
need space between /
> + EXYNOS_DUALRGB_MAIN_CNT(0);
> + } else
This else statement is unnecessary
> + cfg = 0;
> +
> + writel(cfg, &fimd_ctrl->dualrgb);
> +}
> +
> +static void exynos_fimd_set_par(unsigned int win_id)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + /* set window control */
> + cfg = readl(&fimd_ctrl->wincon0 + (win_id * 0x4));
What is 0x4?
> +
> + cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
> + EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
> + EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
> + EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
> +
> + /* DATAPATH is DMA */
> + cfg |= EXYNOS_WINCON_DATAPATH_DMA;
> +
> + /* bpp is 32 */
> + cfg |= EXYNOS_WINCON_WSWP_ENABLE;
> +
> + /* dma burst is 16 */
> + cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
> +
> + /* pixel format is unpacked RGB888 */
> + cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
> +
> + writel(cfg, &fimd_ctrl->wincon0 + (win_id * 0x4));
> + udebug("wincon%d = %x\n", win_id, cfg);
> +
> + /* set window position to x=0, y=0*/
> + cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
> + writel(cfg, &fimd_ctrl->vidosd0a + (win_id * 0x10));
what is 0x10?
> + udebug("window postion left,top = %x\n", cfg);
> +
> + cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
> + EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
> + writel(cfg, &fimd_ctrl->vidosd0b + (win_id * 0x10));
> + udebug("window postion right,bottom= %x\n", cfg);
> +
> + /* set window size for window0*/
> + cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
> + writel(cfg, &fimd_ctrl->vidosd0c + (win_id * 0x10));
> + udebug("vidosd_c%d= %x\n", win_id, cfg);
> +
> + return;
no need return.
> +}
> +
> +static void exynos_fimd_set_buffer_address(unsigned int win_id)
> +{
> + unsigned long start_addr, end_addr;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + start_addr = (unsigned long)lcd_base_addr;
> + end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
> + * pvid->vl_row);
> +
> + writel(start_addr, &fimd_ctrl->vidw00add0b0 + (win_id * 0x10));
> + writel(end_addr, &fimd_ctrl->vidw00add0b1 + (win_id * 0x10));
> +
> + udebug("start addr = %x, end addr = %x\n", start_addr, end_addr);
> +
> + return;
ditto.
> +}
> +
> +static void exynos_fimd_set_clock(vidinfo_t *pvid)
> +{
> + unsigned int cfg = 0, div = 0, remainder, remainder_div;
> + unsigned long pixel_clock, src_clock, max_clock;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> + u64 div64;
> +
> + max_clock = 86 * 1000000;
Please define this constant.
> +
> + if (pvid->dual_lcd_enabled)
> + pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
> + pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
> + pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
> + else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
> + pixel_clock = pvid->vl_freq * pvid->vl_width *
> pvid->vl_height *
> + (pvid->cs_setup + pvid->wr_setup + pvid->wr_act +
> + pvid->wr_hold + 1);
> + } else
need brace.
> + pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
> + pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
> + pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
> +
> + if (get_pll_clk == NULL) {
> + printf("get_pll_clk is null.\n");
> + return;
> + }
Please move this error checking logic to top of function
> + src_clock = get_lcd_clk();
> +
> + cfg = readl(&fimd_ctrl->vidcon0);
> + cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
> + EXYNOS_VIDCON0_CLKVAL_F(0xFF) |
> + EXYNOS_VIDCON0_VCLKEN_MASK | EXYNOS_VIDCON0_CLKDIR_MASK);
> + cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
> + EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
> +
> + if (pixel_clock > max_clock)
> + pixel_clock = max_clock;
> +
> + div64 = (u64)get_lcd_clk();
> +
> + /* get quotient and remainder. */
> + remainder = do_div(div64, pixel_clock);
> + div = (u32) div64;
> +
> + remainder *= 10;
> + remainder_div = remainder / pixel_clock;
> +
> + /* round about one places of decimals. */
> + if (remainder_div >= 5)
> + div++;
> +
> + /* in case of dual lcd mode. */
> + if (pvid->dual_lcd_enabled)
> + div--;
> +
> + cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
> + writel(cfg, &fimd_ctrl->vidcon0);
> +
> + udebug("src_clock = %d, pixel_clock = %d, div = %d\n",
> + src_clock, pixel_clock, div);
> +
> + return;
no need return.
> +}
> +
> +void s3cfb_set_trigger(void)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + cfg = readl(&fimd_ctrl->trigcon);
> +
> + cfg |= 1 << 0 | 1 << 1;
What is bit0 and bit1?
> +
> + writel(cfg, &fimd_ctrl->trigcon);
> +}
> +
> +int s3cfb_is_i80_frame_done(void)
> +{
> + unsigned int cfg = 0;
> + int status;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + cfg = readl(&fimd_ctrl->trigcon);
> +
> + /* frame done func is valid only when TRIMODE[0] is set to 1. */
> + status = (((cfg & (0x1 << 2)) == (0x1 << 2)) ? 1 : 0);
What is 0x1 << 2?
And it should be..
status = cfg & (0x1 << 2) == (0x1 << 2);
or
status = !!(cfg & (0x1 << 2));
> +
> + return status;
> +}
> +
> +static void exynos_fimd_lcd_on(unsigned int win_id)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + /* display on */
> + cfg = readl(&fimd_ctrl->vidcon0);
> + cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
> + writel(cfg, &fimd_ctrl->vidcon0);
> + udebug("vidcon0 = %x\n", cfg);
> +}
> +
> +static void exynos_fimd_window_on(unsigned int win_id)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + /* enable window */
> + cfg = readl(&fimd_ctrl->wincon0 + (win_id * 0x4));
> + cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
> + writel(cfg, &fimd_ctrl->wincon0 + (win_id * 0x4));
> + udebug("wincon%d=%x\n", win_id, cfg);
> +
> + /* evt1 */
> + cfg = readl(&fimd_ctrl->winshmap);
> + cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
> + writel(cfg, &fimd_ctrl->winshmap);
> +}
> +
> +void exynos_fimd_lcd_off(unsigned int win_id)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + cfg = readl(&fimd_ctrl->vidcon0);
> + cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE |
> EXYNOS_VIDCON0_ENVID_F_DISABLE);
> + writel(cfg, &fimd_ctrl->vidcon0);
> +}
> +
> +void exynos_fimd_window_off(unsigned int win_id)
> +{
> + unsigned int cfg = 0;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + cfg = readl(&fimd_ctrl->wincon0 + (win_id * 0x4));
> + cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
> + writel(cfg, &fimd_ctrl->wincon0 + (win_id * 0x4));
> +
> + /* evt1 */
> + cfg = readl(&fimd_ctrl->winshmap);
> + cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
> + writel(cfg, &fimd_ctrl->winshmap);
> +}
> +
> +int exynos_set_auto_cmd_rate(unsigned char cmd_rate, unsigned char ldi)
> +{
> + unsigned int cmd_rate_val;
> + unsigned int i80_if_con_reg_val;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + cmd_rate_val = (cmd_rate == DISABLE_AUTO_FRM) ? (0x0 << 0) :
> + (cmd_rate == PER_TWO_FRM) ? (0x1 << 0) :
> + (cmd_rate == PER_FOUR_FRM) ? (0x2 << 0) :
> + (cmd_rate == PER_SIX_FRM) ? (0x3 << 0) :
> + (cmd_rate == PER_EIGHT_FRM) ? (0x4 << 0) :
> + (cmd_rate == PER_TEN_FRM) ? (0x5 << 0) :
> + (cmd_rate == PER_TWELVE_FRM) ? (0x6 << 0) :
> + (cmd_rate == PER_FOURTEEN_FRM) ? (0x7 << 0) :
> + (cmd_rate == PER_SIXTEEN_FRM) ? (0x8 << 0) :
> + (cmd_rate == PER_EIGHTEEN_FRM) ? (0x9 << 0) :
> + (cmd_rate == PER_TWENTY_FRM) ? (0xa << 0) :
> + (cmd_rate == PER_TWENTY_TWO_FRM) ? (0xb << 0) :
> + (cmd_rate == PER_TWENTY_FOUR_FRM) ? (0xc << 0) :
> + (cmd_rate == PER_TWENTY_SIX_FRM) ? (0xd << 0) :
> + (cmd_rate == PER_TWENTY_EIGHT_FRM) ? (0xe << 0) : (0xf << 0);
> +
> + i80_if_con_reg_val = readl(&fimd_ctrl->i80ifconb0);
> + i80_if_con_reg_val &= ~(0xf << 0);
> + i80_if_con_reg_val |= cmd_rate_val;
> + writel(i80_if_con_reg_val, &fimd_ctrl->i80ifconb0);
> +
> + return 0;
always return 0?
> +}
> +
> +void exynos_fimd_lcd_init(vidinfo_t *vid)
> +{
> + unsigned int cfg = 0, rgb_mode, win_id = 3;
> + struct exynos4_fb *fimd_ctrl =
> + (struct exynos4_fb *)samsung_get_base_fimd();
> +
> + /* store panel info to global variable */
> + pvid = vid;
> +
> + rgb_mode = MODE_RGB_P;
> +
> + if (vid->interface_mode == FIMD_RGB_INTERFACE) {
> + cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
> + writel(cfg, &fimd_ctrl->vidcon0);
> +
> + cfg = readl(&fimd_ctrl->vidcon2);
> + cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
> + EXYNOS_VIDCON2_TVFORMATSEL_MASK |
> + EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
> + cfg |= EXYNOS_VIDCON2_WB_DISABLE;
> + writel(cfg, &fimd_ctrl->vidcon2);
> +
> + /* set polarity */
> + cfg = 0;
> + if (!pvid->vl_clkp)
> + cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
> + if (!pvid->vl_hsp)
> + cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
> + if (!pvid->vl_vsp)
> + cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
> + if (!pvid->vl_dp)
> + cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
> +
> + writel(cfg, &fimd_ctrl->vidcon1);
> +
> + /* set timing */
> + cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
> + cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
> + cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
> + writel(cfg, &fimd_ctrl->vidtcon0);
> + udebug("vidtcon0 = %x\n", cfg);
> +
> +
> + cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
> + cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
> + cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
> +
> + writel(cfg, &fimd_ctrl->vidtcon1);
> + udebug("vidtcon1 = %x\n", cfg);
> +
> + /* set lcd size */
> + cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1);
> + cfg |= EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1);
> +
> + writel(cfg, &fimd_ctrl->vidtcon2);
> + udebug("vidtcon2 = %x\n", cfg);
> +
remove this space
> + }
> +
> + /* set display mode */
> + cfg = readl(&fimd_ctrl->vidcon0);
> + cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
> + cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
> + writel(cfg, &fimd_ctrl->vidcon0);
> +
> + /* set par */
> + exynos_fimd_set_par(win_id);
> +
> + /* set memory address */
> + exynos_fimd_set_buffer_address(win_id);
> +
> + /* set buffer size */
> + cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8);
> + writel(cfg, &fimd_ctrl->vidw00add2 + (win_id * 0x4));
> + udebug("vidaddr_pagewidth = %d\n", cfg);
> +
> + /* set clock */
> + exynos_fimd_set_clock(vid);
> +
> + /* set rgb mode to dual lcd. */
> + if (pvid->dual_lcd_enabled)
> + exynos_fimd_set_dualrgb(1);
> + else
> + exynos_fimd_set_dualrgb(0);
exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled); ?
> +
> + /* display on */
> + exynos_fimd_lcd_on(win_id);
> +
> + /* window on */
> + exynos_fimd_window_on(win_id);
> +
> + udebug("lcd controller init completed.\n");
> +
> + return;
> +}
> +
> +ulong exynos_fimd_calc_fbsize(void)
> +{
> + return pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8);
> +}
> --
Thanks.
Minkyu Kang.
--
from. prom.
www.promsoft.net
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