From: Shiraz Hashim <shiraz.has...@st.com>
UART in u-boot intends to run on 48MHz clock supplied by USB PLL.
Explicitly select the intended clock source.
Signed-off-by: Shiraz Hashim <shiraz.has...@st.com>
Signed-off-by: Amit Virdi <amit.vi...@st.com>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 7 ++++++-
arch/arm/include/asm/arch-spear/spr_misc.h | 2 ++
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c
b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 4dc7d69..8f34aed 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -31,7 +31,7 @@ int arch_cpu_init(void)
{
struct misc_regs *const misc_p =
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
- u32 periph1_clken;
+ u32 periph1_clken, periph_clk_cfg;
periph1_clken = readl(&misc_p->periph1_clken);
@@ -43,6 +43,11 @@ int arch_cpu_init(void)
#if defined(CONFIG_PL011_SERIAL)
periph1_clken |= MISC_UART0ENB;
+
+ periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+ periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+ periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+ writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
#endif
#if defined(CONFIG_DESIGNWARE_ETH)
periph1_clken |= MISC_ETHENB;
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h
b/arch/arm/include/asm/arch-spear/spr_misc.h
index b10c726..384944d 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -110,6 +110,8 @@ struct misc_regs {
/* PERIPH_CLK_CFG value */
#define MISC_GPT3SYNTH 0x00000400
#define MISC_GPT4SYNTH 0x00000800
+#define CONFIG_SPEAR_UART48M 0
+#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
/* PRSC_CLK_CFG value */
/*
--
1.7.2.2
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