Hi,
> this is how the imx-bootlets does it though. It's likely that FSL wants the
> PLL0
> to run from XTAL when doing power configuration?
I was using the FLS bootlets as a reference too, but I have noticed a number of
'mistakes' in that code. For example:
- Busy-indicators aren't considered when reconfiguring PLLs
- They are linked right on top of the expection vectors
- Sloppy printf macros left out <CR>s
So for me it's more of a best effort example than a Reference.
And personally, I'd rather have the CPU running from a rock-solid - yet
slower - xtal, than a sensitive PLL0 when I start tickering with power supplies.
> Maybe clock2pll should be fixed then ?
That's how I started. But properly configuring PLL0 also requires to properly
configure EMI, or the board will hand. And this is exactly what is done in
mx28_mem_init_clock.
clock2pll is broken: It disables PLL bypass without configuring PLL0 first,
or even ungating it. I don't fully understand why it works in normal operation.
Perhaps due to some bus-lag.
I think it is justified to remove it, because what it intends to do, is done
slightly
later by mx28_mem_init_clock. I think FSL reused/shares this code with
other platforms, where no mx28_mem_init_clock is present, but in that case
they do have a bug to fix.
Cheers,
Robert.
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