Add 'clocks' command to print various frequencies such as ARM
frequency, DSP core frequency and DDR frequency. Remove
print_cpuinfo() function as it is no longer required.
Signed-off-by: Manjunath Hadli <manjunath.ha...@ti.com>
Cc: Tom Rini <tr...@ti.com>
---
arch/arm/cpu/arm926ejs/davinci/speed.c | 73 ++++++++++++++++---------------
1 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c
b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 156419b..eb969e5 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -21,6 +21,7 @@
*/
#include <common.h>
+#include <command.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
@@ -114,17 +115,6 @@ int clk_get(enum davinci_clk_ids id)
out:
return pll_out;
}
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
-int print_cpuinfo(void)
-{
- printf("Cores: ARM %d MHz",
- clk_get(DAVINCI_ARM_CLKID) / 1000000);
- printf("\nDDR: %d MHz\n",
- /* DDR PHY uses an x2 input clock */
- clk_get(0x10001) / 1000000);
- return 0;
-}
-#endif
#else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(unsigned pllbase, unsigned offset)
@@ -181,47 +171,60 @@ static unsigned pll_sysclk_mhz(unsigned pll_addr,
unsigned div)
return DIV_ROUND_UP(base, 1000 * pll_div(pll_addr, div));
}
-int print_cpuinfo(void)
+#ifdef DAVINCI_DM6467EVM
+unsigned int davinci_arm_clk_get()
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
+}
+#endif
+
+#if defined(CONFIG_SOC_DM365)
+unsigned int davinci_clk_get(unsigned int div)
+{
+ return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
+}
+#endif
+#endif /* !CONFIG_SOC_DA8XX */
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
+int showclocks(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
{
/* REVISIT fetch and display CPU ID and revision information
* too ... that will matter as more revisions appear.
*/
-#if defined(CONFIG_SOC_DM365)
- printf("Cores: ARM %d MHz",
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+
+ puts("Clock configuration:\n");
+#if defined(CONFIG_SOC_DA8XX)
+ printf("Cores: ARM %d MHz", clk_get(DAVINCI_ARM_CLKID) / 1000000);
+ printf("\nDDR: %d MHz\n",
+ /* DDR PHY uses an x2 input clock */
+ clk_get(0x10001) / 1000000);
#else
- printf("Cores: ARM %d MHz",
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+ unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
+
+#if defined(CONFIG_SOC_DM365)
+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
#endif
+ printf("Cores: ARM %d MHz", pll_sysclk_mhz(pllbase, ARM_PLLDIV));
#ifdef DSP_PLLDIV
printf(", DSP %d MHz",
pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
#endif
+ pllbase = DAVINCI_PLL_CNTRL1_BASE;
+ #if defined(CONFIG_SOC_DM365)
+ pllbase = DAVINCI_PLL_CNTRL0_BASE;
+ #endif
printf("\nDDR: %d MHz\n",
/* DDR PHY uses an x2 input clock */
-#if defined(CONFIG_SOC_DM365)
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
- / 2);
-#else
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
- / 2);
+ pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2);
#endif
return 0;
}
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
+U_BOOT_CMD(clocks, 1, 0, showclocks,
+ "display clocks", "");
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
#endif
-#endif /* !CONFIG_SOC_DA8XX */
--
1.6.2.4
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