[U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when missing USB PHY clock

[Shengzhou Liu]

when missing USB PHY clock and issuing "usb start" at u-boot prompt, writing to
or_portsc register will cause CPU halt. We should check USBGP[PHY_CLK_VALID] bit
at the first time in ehci_hcd_init() to avoid CPU hang in this case.

Signed-off-by: Shengzhou Liu <shengzhou....@freescale.com>
---
 drivers/usb/host/ehci-fsl.c |   22 +++++++++++++++++++---
 1 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index b2d294e..cc29375 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -31,6 +31,18 @@
 #include "ehci.h"
 #include "ehci-core.h"
 
+/* Check USB PHY clock valid */
+static int usb_phy_clk_valid(struct usb_ehci *ehci)
+{
+       if ((!(in_be32(&ehci->control) & PHY_CLK_VALID)) &&
+                       (!in_be32(&ehci->prictrl))) {
+               printf("WARNING: USB PHY clock invalid\n");
+               return 0;
+       } else {
+               return 1;
+       }
+}
+
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
@@ -59,6 +71,9 @@ int ehci_hcd_init(void)
        out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
        out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
 
+       /* Enable interface. */
+       setbits_be32(&ehci->control, USB_EN);
+
        /* Init phy */
        if (hwconfig_sub("usb1", "phy_type"))
                phy_type = hwconfig_subarg("usb1", "phy_type", &len);
@@ -82,6 +97,8 @@ int ehci_hcd_init(void)
                setbits_be32(&ehci->control, UTMI_PHY_EN);
                udelay(1000); /* delay required for PHY Clk to appear */
 #endif
+               if (!usb_phy_clk_valid(ehci))
+                       return -1;
                out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
        } else {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
@@ -89,12 +106,11 @@ int ehci_hcd_init(void)
                setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
                udelay(1000); /* delay required for PHY Clk to appear */
 #endif
+               if (!usb_phy_clk_valid(ehci))
+                       return -1;
                out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
        }
 
-       /* Enable interface. */
-       setbits_be32(&ehci->control, USB_EN);
-
        out_be32(&ehci->prictrl, 0x0000000c);
        out_be32(&ehci->age_cnt_limit, 0x00000040);
        out_be32(&ehci->sictrl, 0x00000001);
-- 
1.6.4


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