The V bit of the c1 register of CP15 should not be cleared
since the SoC has no valid memory at 0x00000000.
Signed-off-by: Christian Riesch <christian.rie...@omicron.at>
Reported-by: Sughosh Ganu <urwithsugh...@gmail.com>
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
Cc: Tom Rini <tr...@ti.com>
---
arch/arm/cpu/arm926ejs/start.S | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index b39ed8a..b350480 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -372,7 +372,10 @@ flush_dcache:
* disable MMU and D cache, and enable I cache
*/
mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
+#ifndef CONFIG_SOC_DA850
+ bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
+#endif
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
--
1.7.0.4
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