Signed-off-by: Daniel Schwierzeck <daniel.schwierz...@googlemail.com>
---
This patch fixes the last broken board when running MAKEALL -a mips.
This board was added by Wolfgang in 2004 and never had a real
maintainer. If no one care about this board, I think it could be dropped.
board/tb0229/flash.c | 3 --
board/tb0229/tb0229.c | 10 ++++---
board/tb0229/vr4131-pci.c | 65 +++++++++++++++++++++++---------------------
3 files changed, 40 insertions(+), 38 deletions(-)
diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c
index 75d7769..ec64e5c 100644
--- a/board/tb0229/flash.c
+++ b/board/tb0229/flash.c
@@ -24,7 +24,6 @@
*/
#include <common.h>
-#include <asm/ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips
*/
@@ -59,8 +58,6 @@ unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
index d3f05b2..9c284f0 100644
--- a/board/tb0229/tb0229.c
+++ b/board/tb0229/tb0229.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/reboot.h>
@@ -26,21 +27,22 @@ void _machine_restart(void)
#if defined(CONFIG_PCI)
static struct pci_controller hose;
-void pci_init_board (void)
+void pci_init_board(void)
{
+ extern void init_vr4131_pci(struct pci_controller *hose);
init_vr4131_pci(&hose);
}
#endif
phys_size_t initdram(int board_type)
{
- return get_ram_size (CONFIG_SYS_SDRAM_BASE, 0x8000000);
+ return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x8000000);
}
-int checkboard (void)
+int checkboard(void)
{
printf("Board: TANBAC TB0229 ");
- printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+ printf("(CPU Speed %d MHz)\n", (int) CPU_CLOCK_RATE / 1000000);
set_io_port_base(0);
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
index 6ff4293..a011391 100644
--- a/board/tb0229/vr4131-pci.c
+++ b/board/tb0229/vr4131-pci.c
@@ -56,8 +56,8 @@ volatile unsigned int *pciconfigdata;
* Access PCI Configuration Register for VR4131
*/
-static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
- u32 * data)
+static int vr4131_pci_config_access(u8 access_type, pci_dev_t dev, int reg,
+ u32 *data)
{
u32 bus;
u32 device;
@@ -73,20 +73,20 @@ static int vr4131_pci_config_access (u8 access_type, u32
dev, u32 reg,
*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
}
- if (access_type == PCI_ACCESS_WRITE) {
+ if (access_type == PCI_ACCESS_WRITE)
*VR4131_PCICONFDREG = *data;
- } else {
+ else
*data = *VR4131_PCICONFDREG;
- }
return (0);
}
-static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+static int vr4131_pci_read_config_byte(struct pci_controller *hose,
+ pci_dev_t dev, int reg, u8 *val)
{
u32 data;
- if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = (data >> ((reg & 3) << 3)) & 0xff;
@@ -95,14 +95,15 @@ static int vr4131_pci_read_config_byte (u32 hose, u32 dev,
u32 reg, u8 * val)
}
-static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+static int vr4131_pci_read_config_word(struct pci_controller *hose,
+ pci_dev_t dev, int reg, u16 *val)
{
u32 data;
if (reg & 1)
return -1;
- if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = (data >> ((reg & 3) << 3)) & 0xffff;
@@ -111,15 +112,15 @@ static int vr4131_pci_read_config_word (u32 hose, u32
dev, u32 reg, u16 * val)
}
-static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
- u32 * val)
+static int vr4131_pci_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int reg, u32 *val)
{
u32 data = 0;
if (reg & 3)
return -1;
- if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_READ, dev, reg, &data))
return -1;
*val = data;
@@ -127,53 +128,55 @@ static int vr4131_pci_read_config_dword (u32 hose, u32
dev, u32 reg,
return (0);
}
-static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+static int vr4131_pci_write_config_byte(struct pci_controller *hose,
+ pci_dev_t dev, int reg, u8 val)
{
u32 data = 0;
- if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_READ, dev, reg, &data))
return -1;
data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
((reg & 3) << 3));
- if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return 0;
}
-static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+static int vr4131_pci_write_config_word(struct pci_controller *hose,
+ pci_dev_t dev, int reg, u16 val)
{
u32 data = 0;
if (reg & 1)
return -1;
- if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_READ, dev, reg, &data))
return -1;
data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
((reg & 3) << 3));
- if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return 0;
}
-static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+static int vr4131_pci_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int reg, u32 val)
{
u32 data;
- if (reg & 3) {
+ if (reg & 3)
return -1;
- }
data = val;
- if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+ if (vr4131_pci_config_access(PCI_ACCESS_WRITE, dev, reg, &data))
return -1;
return (0);
@@ -184,7 +187,7 @@ static int vr4131_pci_write_config_dword (u32 hose, u32
dev, u32 reg, u32 val)
* Initialize VR4131 PCIU
*/
-vr4131_pciu_init ()
+static void vr4131_pciu_init(void)
{
/* PCI clock */
*VR4131_PCICLKSELREG = 0x00000002;
@@ -211,28 +214,28 @@ vr4131_pciu_init ()
* Initialize Module
*/
-void init_vr4131_pci (struct pci_controller *hose)
+void init_vr4131_pci(struct pci_controller *hose)
{
hose->first_busno = 0;
hose->last_busno = 0xff;
- vr4131_pciu_init (); /* Initialize VR4131 PCIU */
+ vr4131_pciu_init(); /* Initialize VR4131 PCIU */
/* PCI memory space #1 */
- pci_set_region (hose->regions + 0,
+ pci_set_region(hose->regions + 0,
0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
/* PCI memory space #2 */
- pci_set_region (hose->regions + 1,
+ pci_set_region(hose->regions + 1,
0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
/* PCI I/O space */
- pci_set_region (hose->regions + 2,
+ pci_set_region(hose->regions + 2,
0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
/* System memory space */
- pci_set_region (hose->regions + 3,
+ pci_set_region(hose->regions + 3,
0x00000000,
0x80000000,
0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
@@ -246,9 +249,9 @@ void init_vr4131_pci (struct pci_controller *hose)
hose->write_word = vr4131_pci_write_config_word;
hose->write_dword = vr4131_pci_write_config_dword;
- pci_register_hose (hose);
+ pci_register_hose(hose);
- hose->last_busno = pci_hose_scan (hose);
+ hose->last_busno = pci_hose_scan(hose);
return;
}
--
1.7.8
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