Re: [U-Boot] [PATCH V2 5/6] i.mx: fsl_esdhc: add the i.mx6q support

[Stefano Babic]

On 18/11/2011 08:11, Jason Liu wrote:
> The mmc host controller on the i.mx6q is called usdhc which
> is redesigned based on the freescale esdhc controller.
> 
> The usdhc controller is almost compatible with esdhc except
> it adds one mix register to support debug/SD3.0 and move
> the low bit 0-6 of XFERTYP register to the mix control reg
> low bit 0-6. Thus on i.mx6q, we have the following compared
> with the previous soc: (can refer to RM of chapter 56.3.3)
> 
> i.mx6q:
> mix control:
> bit 31 - bit 7: Added for debug/SD3.0 support
> bit 6  - bit 0: move in the XFERTYP register bit 6-0 on previous soc
> XFERTYP register:
> bit 31 - bit 7: the same as before,
> bit 6  - bit 0: no-use
> 
> previous soc
> mix control: no
> XFERTYP register:
> bit 31 - bit 0: xfertype information
> 
> Signed-off-by: Jason Liu <jason....@linaro.org>
> CC:Stefano Babic <sba...@denx.de>
> Acked-by: Stefano Babic <sba...@denx.de>
> ---
> v2: extend the commit message by adding mix/xtertype register change
>     remove one #ifdef as Marek suggested
>     change the print of USDHC/ESDHC to SDHC
> ---
>  drivers/mmc/fsl_esdhc.c |   12 +++++++++---
>  1 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index ec953f0..ddd1b4c 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -58,7 +58,8 @@ struct fsl_esdhc {
>       uint    autoc12err;
>       uint    hostcapblt;
>       uint    wml;
> -     char    reserved1[8];
> +     uint    mixctrl;
> +     char    reserved1[4];
>       uint    fevt;
>       char    reserved2[168];
>       uint    hostver;
> @@ -298,8 +299,13 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 
> struct mmc_data *data)
>  
>       /* Send the command */
>       esdhc_write32(&regs->cmdarg, cmd->cmdarg);
> +#if defined(CONFIG_FSL_USDHC)
> +     esdhc_write32(&regs->mixctrl,
> +     (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
> +     esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
> +#else
>       esdhc_write32(&regs->xfertyp, xfertyp);
> -
> +#endif
>       /* Wait for the command to complete */
>       while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
>               ;
> @@ -482,7 +488,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg 
> *cfg)
>  
>       mmc = malloc(sizeof(struct mmc));
>  
> -     sprintf(mmc->name, "FSL_ESDHC");
> +     sprintf(mmc->name, "FSL_SDHC");
>       regs = (struct fsl_esdhc *)cfg->esdhc_base;

Jason,

I have no issues about this patch, but it was not forwarded to Andy (MMC
Maintainer).

>From my site:

Acked-by: Stefano Babic <sba...@denx.de>

Best regards,
Stefano Babic


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