On Wed, 16 Nov 2011 15:36:25 +0800 <chang-ming.hu...@freescale.com> wrote:
> From: Jerry Huang <chang-ming.hu...@freescale.com> > > In the current u-boot code, the value of these fields are the reserved > value (0b100), through the signal integrity measurement on freescale's > board with these reserved setting, the signal eye is out of the recommended > spec for non-transition amplitude at 500mV nominal. > According to the errata for MPC8379E, we should make a change to the > recommended setting from essentially nothing at this time to 0b001 for SATA. what erratum #? How am I supposed to know this won't break the 8308 boards that share this file? > + /* Configure SRDSCR0 */ > + tmp = in_be32(regs + FSL_SRDSCR0_OFFS); > + tmp &= ~FSL_SRDSCR0_TXEQA_MASK; > + tmp |= FSL_SRDSCR0_TXEQA_SATA; > + tmp &= ~FSL_SRDSCR0_TXEQE_MASK; > + tmp |= FSL_SRDSCR0_TXEQE_SATA; > + out_be32(regs + FSL_SRDSCR0_OFFS, tmp); > + use clrsetbits_be32 Kim _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
