On 11/02/2011 05:16 PM, Stefano Babic wrote:
> On 11/02/2011 05:03 PM, Jana Rapava wrote:
>>
>> Ok, so non-board-specific parts should go into ./arch/arm/cpu/armv7/mx5/
>> and board-specific callbacks should stay here? Do I understand you well?
>
> Yes, I think so
>
>>
>>>
>>> I don't want to block on that issue, so if it simplifies you a
>>> further ULPI patches submission - I don't care if you leave it here
>>> and in the next patch set move to a common location.
>>>
>>>
>> Thanks.
>
> Anyway, as we agree, it is really better to do now the right thing as to
> postpone.
I'm want to provide USB support for mx53loco and maybe mx51evk,
similar to what Jana is doing. Following the "drivers/usb/host/ehci mxc.c"
example, I tried to do it the generic way by implementing
"drivers/usb/host/ehci-mx5.c". Not sure if it's the better approach as
a board specific initialization/reset might be required for some boards.
Therefore board specific callbacks would make sense. I have attached my
patch below for review and comments.
Thanks,
Wolfgang,
>From b88a75699646583fa368cc40eb000b773bea9e1d Mon Sep 17 00:00:00 2001
From: Wolfgang Grandegger <w...@denx.de>
Date: Mon, 7 Nov 2011 15:48:00 +0100
Subject: [PATCH] mx53loco: USB EHCI for MX5
Signed-off-by: Wolfgang Grandegger <w...@denx.de>
---
arch/arm/cpu/armv7/mx5/clock.c | 72 ++++++++++++
arch/arm/include/asm/arch-mx5/clock.h | 5 +
arch/arm/include/asm/arch-mx5/crm_regs.h | 3 +
arch/arm/include/asm/arch-mx5/imx-regs.h | 33 ++++++
arch/arm/include/asm/arch-mx5/mx5x_pins.h | 4 +
board/freescale/mx53loco/mx53loco.c | 11 ++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-mx5.c | 174 +++++++++++++++++++++++++++++
include/configs/mx53loco.h | 13 ++
9 files changed, 316 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/ehci-mx5.c
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 0769a64..c8dad17 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -50,6 +50,78 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+void set_usboh3_clk(void)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->cscmr1) &
+ ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+ reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+ writel(reg, &mxc_ccm->cscmr1);
+
+ reg = readl(&mxc_ccm->cscdr1);
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
+ reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
+ reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
+ reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
+
+ writel(reg, &mxc_ccm->cscdr1);
+}
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->CCGR2);
+ if (enable)
+ reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+ else
+ reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+ writel(reg, &mxc_ccm->CCGR2);
+}
+
+void set_usb_phy1_clk(void)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+
+void enable_usb_phy1_clk(unsigned char enable)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->CCGR4);
+ if (enable)
+ reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+ else
+ reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
+ writel(reg, &mxc_ccm->CCGR4);
+}
+
+void set_usb_phy2_clk(void)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+
+void enable_usb_phy2_clk(unsigned char enable)
+{
+ unsigned int reg;
+
+ reg = readl(&mxc_ccm->CCGR4);
+ if (enable)
+ reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+ else
+ reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
+ writel(reg, &mxc_ccm->CCGR4);
+}
+
/*
* Calculate the frequency of PLLn.
*/
diff --git a/arch/arm/include/asm/arch-mx5/clock.h
b/arch/arm/include/asm/arch-mx5/clock.h
index 1f8a537..ea972a3 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -40,4 +40,9 @@ u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+void set_usb_phy2_clk(void);
+void enable_usb_phy2_clk(unsigned char enable);
+void set_usboh3_clk(void);
+void enable_usboh3_clk(unsigned char enable);
+
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h
b/arch/arm/include/asm/arch-mx5/crm_regs.h
index fcc0e36..7972147 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -195,7 +195,10 @@ struct mxc_ccm_reg {
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
+#define MXC_CCM_CCGR4_CG5_OFFSET 10
+#define MXC_CCM_CCGR4_CG6_OFFSET 12
#define MXC_CCM_CCGR5_CG5_OFFSET 10
+#define MXC_CCM_CCGR2_CG14_OFFSET 28
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index d069209..1ac9705 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -134,6 +134,39 @@
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
/*
+ * USB
+ */
+#define MXC_USBCTRL_OFFSET 0
+#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
+#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
+#define MXC_USBH2CTRL_OFFSET 0x14
+
+/* Values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
+#define MXC_EHCI_FORCE_FS (1 << 24)
+#define MXC_EHCI_UTMI_8BIT (0 << 28)
+#define MXC_EHCI_UTMI_16BIT (1 << 28)
+#define MXC_EHCI_SERIAL (1 << 29)
+#define MXC_EHCI_MODE_UTMI (0 << 30)
+#define MXC_EHCI_MODE_PHILIPS (1 << 30)
+#define MXC_EHCI_MODE_ULPI (2 << 30)
+#define MXC_EHCI_MODE_SERIAL (3 << 30)
+
+/* Values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
+#define MXC_EHCI_INTERFACE_MASK (0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
+#define MXC_EHCI_TTL_ENABLED (1 << 6)
+
+#define MXC_EHCI_INTERNAL_PHY (1 << 7)
+#define MXC_EHCI_IPPUE_DOWN (1 << 8)
+#define MXC_EHCI_IPPUE_UP (1 << 9)
+
+/*
* WEIM CSnGCR1
*/
#define CSEN 1
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
index 4e3a31b..3978bd5 100644
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
@@ -25,6 +25,10 @@
#ifndef __ASSEMBLY__
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
+
/*
* In order to identify pins more effectively, each mux-controlled pin's
* enumerated value is constructed in the following way:
diff --git a/board/freescale/mx53loco/mx53loco.c
b/board/freescale/mx53loco/mx53loco.c
index 156f8b5..b867714 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -83,6 +83,16 @@ static void setup_iomux_uart(void)
PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
+static void setup_usb_h1(void)
+{
+ /* request VBUS power enable pin, GPIO[8}, gpio7 */
+ mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
+
+ gpio_direction_output(IMX_GPIO_NR(7, 8), 0);
+
+ gpio_set_value(IMX_GPIO_NR(7, 8), 1);
+}
+
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
@@ -282,6 +292,7 @@ int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
+ setup_usb_h1();
return 0;
}
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 51b2494..60632ba 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -41,6 +41,7 @@ else
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
endif
COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
+COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
new file mode 100644
index 0000000..9f3e654
--- /dev/null
+++ b/drivers/usb/host/ehci-mx5.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <dan...@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <errno.h>
+#include <linux/compiler.h>
+#include <usb/ehci-fsl.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx5x_pins.h>
+
+#include "ehci.h"
+#include "ehci-core.h"
+
+#define MX5_USBOTHER_REGS_OFFSET 0x800
+
+
+#define MXC_OTG_OFFSET 0
+#define MXC_H1_OFFSET 0x200
+#define MXC_H2_OFFSET 0x400
+
+/* USB_CTRL */
+#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+
+/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+
+#define MXC_USBCMD_OFFSET 0x140
+
+int mxc_set_usbcontrol(int port, unsigned int flags)
+{
+ unsigned int v;
+ void __iomem *usb_base;
+ void __iomem *usbotg_base;
+ void __iomem *usbother_base;
+ int ret = 0;
+
+ usb_base = OTG_BASE_ADDR;
+
+ switch (port) {
+ case 0: /* OTG port */
+ usbotg_base = usb_base + MXC_OTG_OFFSET;
+ break;
+ case 1: /* Host 1 port */
+ usbotg_base = usb_base + MXC_H1_OFFSET;
+ break;
+ case 2: /* Host 2 port */
+ usbotg_base = usb_base + MXC_H2_OFFSET;
+ break;
+ default:
+ return -EINVAL;
+ }
+ usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+ switch (port) {
+ case 0: /* OTG port */
+ if (flags & MXC_EHCI_INTERNAL_PHY) {
+ v = __raw_readl(usbother_base +
+ MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ /* OC/USBPWR is not used */
+ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+ else
+ /* OC/USBPWR is used */
+ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+ __raw_writel(v, usbother_base +
+ MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v |= MXC_OTG_UCTRL_OPM_BIT;
+ else
+ v &= ~MXC_OTG_UCTRL_OPM_BIT;
+ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+ }
+ break;
+ case 1: /* Host 1 Host ULPI */
+ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ else
+ v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */
+ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+
+ v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+ else
+ v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+ __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+ break;
+ case 2: /* Host 2 ULPI */
+ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+ else
+ v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */
+
+ __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+ break;
+ }
+
+error:
+ return ret;
+}
+
+int ehci_hcd_init(void)
+{
+ struct usb_ehci *ehci;
+#ifdef CONFIG_MX53
+ struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
+ /* derive USB PHY clock multiplexer from PLL3 */
+ reg |= 1 << 26;
+ __raw_writel(reg, &sc_regs->cscmr1);
+#endif
+
+ set_usboh3_clk();
+ enable_usboh3_clk(1);
+ set_usb_phy2_clk();
+ enable_usb_phy2_clk(1);
+
+ udelay(80);
+
+ ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+ (0x200 * CONFIG_MXC_USB_PORT));
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ hcor = (struct ehci_hcor *)((uint32_t)hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ setbits_le32(&ehci->usbmode, CM_HOST);
+
+#ifdef CONFIG_MX53
+ setbits_le32(&ehci->portsc, USB_EN);
+ __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
+#endif
+
+ mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
+
+ udelay(10000);
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index c3e4e13..aad7368 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -181,4 +181,17 @@
#define CONFIG_OF_LIBFDT
+/* USB support */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_UTMI | MXC_EHCI_UTMI_16BIT)
+#define CONFIG_MXC_USB_FLAGS 0
+
#endif /* __CONFIG_H */
--
1.7.6.4
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