Hi Simon, On 02/11/11 04:22, Simon Glass wrote: > + /* Need to reset PHY -> 500ms reset */ > + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; > + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | > + AT91_RSTC_MR_URSTEN, &rstc->mr); > + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
You don't actually need to reset the PHY for 500ms, only 100us, so the AT91_RSTC_MR_ERSTL(13) can be replaced with AT91_RSTC_MR_ERSTL(0), which give you the minimum delay (62ms I think). Regards, Andre -- Bluewater Systems - An Aiotec Company Andre Renaud an...@bluewatersys.com 5 Amuri Park, 404 Barbadoes St www.bluewatersys.com PO Box 13 889, Christchurch 8013 www.aiotec.co.nz New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
