Hi Albert, On Thu, Oct 27, 2011 at 10:09 PM, Albert ARIBAUD <albert.u.b...@aribaud.net> wrote: > Le 28/10/2011 03:43, Simon Glass a écrit : > >> The test was >> >> mrc p15, 0, r0, c0, c0, 0 @ get ID register >> and r0, r0, #0xf0000 @ get architecture >> cmp r0, #0xf0000 @ check for> ARMv6 >> movne pc, lr @ else skip cache init >> >> Unfortunately I think it is a plain ARM7TDMI with no CP15. > > What about other fields in r0 right after mrc?
I don't really understand that sentence, sorry. The ARM7TDMI does not have a CP15 and aborts if I try to access it. Just in case there is something odd going on I checked with DSTREAM / RVdebug and it definitely doesn't have a CP15. [as Ford Prefect would say, I counted them twice] The simplest thing I have been able to think of that does not involve exceptions, differing instruction behaviour, doing the init later or putting in some Tegra-specific code is to check for the existence of the Q bit in the CPSR (actually APSR on ARMv7). This does seem to work and I have verified both in my old 1996 ARM ARM DDI 0100B and the ARMv7-A one (DDI 0406B) that from an architecture point of view this should work. The Q bit is RAZ on ARMv4T. I believe this will cope with the Cortex-A7 / A-15 combinations and possibly even Cortex-R4 / A-15 although I have not tested this. I suppose we can deal with this when it becomes an issue. So I have redone this one patch with that in mind, and adjusted the series slightly to fit with this. I will resend it when it completes MAKEALL. I hope that this resolves the matter, but if not(!), I would very much appreciate it if you could send through some actual pseudo code showing what you are looking for, to avoid any confusion. Thanks, Simon > >> Regards, >> Simon > > Amicalement, > -- > Albert. > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
