From: Manjunath Hadli <manjunath.ha...@ti.com> revert commit 913a39e9aa4d935948d41cd727d53f5878414a77 as the disabling of cache need not be done explicitly. Subsequent patches to new cache management framework has fixed it. EMAC issue with cache coherency still exists when cahces are enabled.
Signed-off-by: Manjunath Hadli <manjunath.ha...@ti.com> --- include/configs/davinci_dvevm.h | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 2e56501..4742658 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -59,9 +59,6 @@ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SOC_DM644X -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_L2CACHE_OFF /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ -- 1.6.2.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
