On Aug 30, 2011, at 6:04 PM, Kumar Gala wrote: > The P2041RDB has almost identical setup for TLB, LAWS, and PCI with > other P-Series CoreNet platforms. > > The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the > CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the > TLB and LAW setup tables. > > Signed-off-by: Kumar Gala <ga...@kernel.crashing.org> > --- > board/freescale/common/Makefile | 1 + > board/freescale/common/p_corenet/law.c | 5 ++ > board/freescale/common/p_corenet/tlb.c | 7 ++ > board/freescale/p2041rdb/Makefile | 3 - > board/freescale/p2041rdb/law.c | 37 ---------- > board/freescale/p2041rdb/pci.c | 39 ---------- > board/freescale/p2041rdb/tlb.c | 123 -------------------------------- > 7 files changed, 13 insertions(+), 202 deletions(-) > delete mode 100644 board/freescale/p2041rdb/law.c > delete mode 100644 board/freescale/p2041rdb/pci.c > delete mode 100644 board/freescale/p2041rdb/tlb.c
applied to 85xx 'next' - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
