The structure and PLL defines are added to
the imx-regs.h file and dropped from board
header files.
Signed-off-by: Stefano Babic <sba...@denx.de>
---
arch/arm/include/asm/arch-mx35/imx-regs.h | 30 +++++++++++++++++++++++++++++
board/freescale/mx35pdk/mx35pdk.h | 18 -----------------
2 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h
b/arch/arm/include/asm/arch-mx35/imx-regs.h
index e741fb0..08fd2d5 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -147,6 +147,19 @@
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
+#define _PLL_BRM(x) ((x) << 31)
+#define _PLL_PD(x) (((x) - 1) << 26)
+#define _PLL_MFD(x) (((x) - 1) << 16)
+#define _PLL_MFI(x) ((x) << 10)
+#define _PLL_MFN(x) (x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+ (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+ _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
@@ -286,6 +299,23 @@ struct wdog_regs {
u16 wmcr; /* Misc Control */
};
+struct esdc_regs {
+ u32 esdctl0;
+ u32 esdcfg0;
+ u32 esdctl1;
+ u32 esdcfg1;
+ u32 esdmisc;
+ u32 reserved[4];
+ u32 esdcdly[5];
+ u32 esdcdlyl;
+};
+
+#define ESDC_MISC_RST (1 << 1)
+#define ESDC_MISC_MDDR_EN (1 << 2)
+#define ESDC_MISC_MDDR_DL_RST (1 << 3)
+#define ESDC_MISC_DDR_EN (1 << 8)
+#define ESDC_MISC_DDR2_EN (1 << 9)
+
/*
* NFMS bit in RCSR register for pagesize of nandflash
*/
diff --git a/board/freescale/mx35pdk/mx35pdk.h
b/board/freescale/mx35pdk/mx35pdk.h
index 409aeb2..6aeb218 100644
--- a/board/freescale/mx35pdk/mx35pdk.h
+++ b/board/freescale/mx35pdk/mx35pdk.h
@@ -59,24 +59,6 @@
#define CCM_CCMR_CONFIG 0x003F4208
#define CCM_PDR0_CONFIG 0x00801000
-#define PLL_BRM_OFFSET 31
-#define PLL_PD_OFFSET 26
-#define PLL_MFD_OFFSET 16
-#define PLL_MFI_OFFSET 10
-
-#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET)
-#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET)
-#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET)
-#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET)
-#define _PLL_MFN(x) (x)
-#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
- (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
- _PLL_MFN(mfn))
-
-#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
-#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
-#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
-
/* MEMORY SETTING */
#define ESDCTL_0x92220000 0x92220000
#define ESDCTL_0xA2220000 0xA2220000
--
1.7.1
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