Wolfgang Denk wrote:
> Dear Michal Simek,
>
> In message <4e607a0b.3040...@monstr.eu> you wrote:
>>>>>> +static void sdma_out_be32(struct ll_priv *priv, u32 offset, u32 val)
>>>>>> +{
>>>>>> + if (priv->mode & DCR_BIT)
>>>>>> + mtdcr_local(priv->ctrl + offset, val);
>>>>>> + else
>>>>>> + out_be32((u32 *)(priv->ctrl + offset * 4), val);
>>>>>> +}
> ...
>> On PPC system with DCR is special connection between memory controller
>> through DCR bus. Handling is done
>> with mfdcr_local and mtdcr_local functions.
>>
>> DMA : Sdma address ranges
>> (www.xilinx.com/support/documentation/user_guides/ug200.pdf page 261 and 299)
>> 0 : 0x80-0x90
>> 1 : 0x98-0xA8
>> 2 : 0xB0-0xC0
>> 3 : 0xC8-0xD8
>>
>> The first reg for DMA2 accessed trough DCR is at 0xB0, the second at 0xB1,
>> etc..
>
> This is indeed a good example, as it shows how terribly broken your
> code is.
>
> See function sdma_out_be32() above. It is suppose to write a 32 bit
> value ("u32 val") as a 32 bit entity in big endian mode ("_be32") to
> some device register - but the register addresses are (1) not aligned
> to 32 bit boundaries and (2) not even 32 bits apart.
I think you misunderstand what there is written.
For DCR is register address with offset + 0x1 but still you are writing there
32bit values. It is not direct access.
and it is not any unaligned access at all. But bus access it will be unaligned
access but not for DCR.
DCR is defined just for PPC right now because none wanted to do it for
Microblaze.
Regards,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
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