On 08/30/2011 03:54 PM, Fabio Estevam wrote:
> Print the source of reset during boot.
>
> Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
> ---
> arch/arm/cpu/arm926ejs/mx25/generic.c | 25 ++++++++++++++++++++++++-
> 1 files changed, 24 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c
> b/arch/arm/cpu/arm926ejs/mx25/generic.c
> index a4e8c14..047e49d 100644
> --- a/arch/arm/cpu/arm926ejs/mx25/generic.c
> +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
> @@ -130,6 +130,28 @@ u32 get_cpu_rev(void)
> return system_rev;
> }
>
> +static char *get_reset_cause(void)
> +{
> + /* read RCSR register from CCM module */
> + struct ccm_regs *ccm =
> + (struct ccm_regs *)IMX_CCM_BASE;
> +
> + u32 cause = readl(&ccm->rcsr) & 0x0f;
> +
> + switch (cause) {
> + case 0x0000:
> + return "POR";
> + case 0x0001:
> + return "RST";
> + case 0x0002:
> + return "WDOG";
> + case 0x0006:
> + return "JTAG";
> + default:
> + return "unknown reset";
> + }
> +}
Can you help me interpreting the manual ? I see in MX25 RM:
REST
Reset status bits. Shows what caused the most recent reset to the
system.Otherwise, the last signal that
is released is honored.
0000 POR reset
0001 Reset In reset.
xx10 WDOG reset
x1x0 SOFT RESET
1xx0 JTAG SW RESET
The code for JTAG seems wrong, should be at 0x08. It sounds me odd that
some bits are not fixed. According to the manual, we should check the
single bits, becase for example a WDOG reset can be identified not only
by 0x02, but also by 0x06, 0x0a, 0x0E..
Best regards,
Stefano Babic
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