On 08/10/2011 10:33 PM, Eric Jarrige wrote: > Improve PLL freq computation by using the full resolution of the PLL registers
Hi Eric, > + return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1)); > +} > > - return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + > (mfn<<10)/(mfd+1)))/(pd+1); Please run checkpatch on your patches for V2. I have not yet done, but this line will report missing spaces. Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
