Architecture includes.
# new file: arch/m68k/include/asm/immap_5307.h
# new file: arch/m68k/include/asm/m5307.h
Signed-off-by: Angelo Dureghello <sysa...@gmail.com>
---
diff --git a/arch/m68k/include/asm/immap_5307.h
b/arch/m68k/include/asm/immap_5307.h
new file mode 100644
index 0000000..cb58297
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -0,0 +1,78 @@
+/*
+ * MCF5307 Internal Memory Map
+ *
+ * Copyright (c) 2011 Angelo Dureghello <sysa...@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5307__
+#define __IMMAP_5307__
+
+#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200)
+
+typedef struct csm {
+ u16 csar0; /* Chip-select Address */
+ u16 res0a;
+ u32 csmr0; /* Chip-select Mask */
+ u16 res0b;
+ u16 cscr0; /* Chip-select Control */
+ u16 csar1;
+ u16 res1a;
+ u32 csmr1;
+ u16 res1b;
+ u16 cscr1;
+ u16 csar2;
+ u16 res2a;
+ u32 csmr2;
+ u16 res2b;
+ u16 cscr2;
+ u16 csar3;
+ u16 res3a;
+ u32 csmr3;
+ u16 res3b;
+ u16 cscr3;
+ u16 csar4;
+ u16 res4a;
+ u32 csmr4;
+ u16 res4b;
+ u16 cscr4;
+ u16 csar5;
+ u16 res5a;
+ u32 csmr5;
+ u16 res5b;
+ u16 cscr5;
+ u16 csar6;
+ u16 res6a;
+ u32 csmr6;
+ u16 res6b;
+ u16 cscr6;
+ u16 csar7;
+ u16 res7a;
+ u32 csmr7;
+ u16 res7b;
+ u16 cscr7;
+} csm_t;
+
+#endif /* __IMMAP_5307__ */
diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h
new file mode 100644
index 0000000..edb1bf2
--- /dev/null
+++ b/arch/m68k/include/asm/m5307.h
@@ -0,0 +1,119 @@
+/*
+ * mcf5307.h -- Definitions for Motorola Coldfire 5307
+ *
+ * Copyright (c) 2011 Angelo Dureghello <sysa...@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef mcf5307_h
+#define mcf5307_h
+/****************************************************************************/
+
+/*
+ * useful definitions for reading/writing MBAR offset memory
+ */
+#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR +
x))
+#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR +
x)) = y
+#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR
+ x)) = y
+#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR +
x)) = y
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 4096 /* RAMBAR - 4k */
+
+/*
+ * Define the 5249 SIM register set addresses.
+ */
+
+/*****************
+ ***** MBAR *****
+ *****************/
+#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */
+#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
+#define MCFSIM_PLLCR 0x08 /* PLL Control register */
+#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
+
+#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
+#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
+
+#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
+
+/*
+ * Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
+#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
+#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
+#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
+/* XXX - If needed, DMA ICRs go here */
+
+/*
+ * Bit definitions for the ICR family of registers.
+ */
+#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
+#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
+#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
+#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
+#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
+#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
+#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
+#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
+#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
+
+#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
+#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
+#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
+#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
+
+/*
+ * Macros to read/set IMR register. It is 32 bits on the 5307.
+ */
+
+#define mcf_getimr() \
+ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
+
+#define mcf_setimr(imr) \
+ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
+
+#endif /* mcf5307_h */
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