On Thu, 2026-07-09 at 16:34 +0200, INgo Rah wrote:
> The Phytec Tauri L is sold with multiple memory configurations beyond the
> base 2 GB variant. To support these alternative capacities seamlessly,
> read the physical memory size directly from the EEPROM of the underlying
> phyCORE module and apply the appropriate DDR timing parameters at runtime.
>
> Alternatively, a fixed memory configuration can still be enforced via a
> dedicated Kconfig option if dynamic detection is not desired.
>
> Note that while U-Boot correctly discovers the full physical memory bank,
> the device tree excludes the memory beyond 3 GB (below the 4 GB boundary).
> This ensures that U-Boot allocations and early EFI staging buffers remain
> safe from 32-bit interconnect DMA limitations inherent to some i.MX8MM
> IP blocks.
>
> Signed-off-by: INgo Rah <[email protected]>
> Reviewed-by: Gregor Herburger <[email protected]>
> Reviewed-by: Benedikt Spranger <[email protected]>
> ---
> arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi | 23 +++++++++
> board/phytec/phycore_imx8mm/Kconfig | 65
> +++++++++++++++++++++++++
> board/phytec/phycore_imx8mm/phycore-imx8mm.c | 18 +++++++
> board/phytec/phycore_imx8mm/spl.c | 56 ++++++++++++++++++++-
> configs/imx8mm-phygate-tauri-l_defconfig | 1 +
> include/configs/phycore_imx8mm.h | 5 +-
> 6 files changed, 165 insertions(+), 3 deletions(-)
>
[...]
> diff --git a/configs/imx8mm-phygate-tauri-l_defconfig
> b/configs/imx8mm-phygate-tauri-l_defconfig
> index 9dc7fe21820..3ae92ff09f6 100644
> --- a/configs/imx8mm-phygate-tauri-l_defconfig
> +++ b/configs/imx8mm-phygate-tauri-l_defconfig
> @@ -4,6 +4,7 @@ CONFIG_TEXT_BASE=0x40200000
> CONFIG_SYS_MALLOC_LEN=0x2000000
> CONFIG_SPL_GPIO=y
> CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_PHYTEC_SOM_DETECTION=y
> CONFIG_ENV_SIZE=0x10000
> CONFIG_ENV_OFFSET=0x3C0000
> CONFIG_DM_GPIO=y
> diff --git a/include/configs/phycore_imx8mm.h
> b/include/configs/phycore_imx8mm.h
> index 20e2ab832ee..d4571cc6f39 100644
> --- a/include/configs/phycore_imx8mm.h
> +++ b/include/configs/phycore_imx8mm.h
> @@ -28,6 +28,7 @@
> #define CFG_SYS_SDRAM_BASE 0x40000000
>
> #define PHYS_SDRAM 0x40000000
> -#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
> -
> +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
> +#define PHYS_SDRAM_2 0x100000000
> +#define PHYS_SDRAM_2_SIZE SZ_1G /* 4GB DDR */
I think this needs a similar solution to
commit 3d634b0b4460 ("board: gateworks: venice: switch to 2-bank dram config")
Yannic
> #endif /* __PHYCORE_IMX8MM_H */
