MT8189 already shares a single U_BOOT_DRIVER across all its clock gate controllers, passing the per-controller gate table through the driver data via a dedicated struct mt8189_gate_clk_data.
Now that struct mtk_clk_tree can describe the gates directly, drop that bespoke helper: give each controller its own struct mtk_clk_tree (.gates/.num_gates/.gates_offs) and use the generic mtk_clk_topckgen_ops. The gate offset, previously computed at runtime from the first gate ID, is now encoded statically in each tree. This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which are scheduled for removal. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> --- drivers/clk/mediatek/clk-mt8189.c | 64 +++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index cf5c4fffe7c..562e55078a0 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -1970,11 +1970,6 @@ static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = { .type = MTK_CLK_TREE_VLP_CK, }; -static const struct mtk_clk_tree mt8189_clk_tree = { - .ext_clk_rates = ext_clock_rates, - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), -}; - static const struct udevice_id mt8189_apmixed[] = { { .compatible = "mediatek,mt8189-apmixedsys", }, { } @@ -1990,32 +1985,31 @@ static const struct udevice_id mt8189_vlpckgen[] = { { } }; -struct mt8189_gate_clk_data { - const struct mtk_gate *gates; - int num_gates; -}; - -#define GATE_CLK_DATA(name) \ -static const struct mt8189_gate_clk_data name##_data = { \ - .gates = name, .num_gates = ARRAY_SIZE(name) \ +#define GATE_CLK_TREE(_name, _gates_offs) \ +static const struct mtk_clk_tree _name##_tree = { \ + .ext_clk_rates = ext_clock_rates, \ + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), \ + .gates = _name, \ + .num_gates = ARRAY_SIZE(_name), \ + .gates_offs = _gates_offs, \ } -GATE_CLK_DATA(perao_clks); -GATE_CLK_DATA(imp_clks); -GATE_CLK_DATA(mm_clks); -GATE_CLK_DATA(mminfra_config_clks); -GATE_CLK_DATA(ufs_config_ao_clks); -GATE_CLK_DATA(ufs_config_pdn_clks); -GATE_CLK_DATA(vlpcfg_ao_clks); +GATE_CLK_TREE(perao_clks, CLK_PERAO_UART0); +GATE_CLK_TREE(imp_clks, CLK_IMPE_I2C0); +GATE_CLK_TREE(mm_clks, CLK_MM_DISP_OVL0_4L); +GATE_CLK_TREE(mminfra_config_clks, CLK_MMINFRA_GCE_D); +GATE_CLK_TREE(ufs_config_ao_clks, CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM); +GATE_CLK_TREE(ufs_config_pdn_clks, CLK_UFSCFG_REG_UFSHCI_UFS); +GATE_CLK_TREE(vlpcfg_ao_clks, CLK_VLPCFG_REG_SCP); static const struct udevice_id of_match_mt8189_clk_gate[] = { - { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data }, - { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data }, - { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data }, - { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data }, - { .compatible = "mediatek,mt8189-ufscfg-ao", .data = (ulong)&ufs_config_ao_clks_data }, - { .compatible = "mediatek,mt8189-ufscfg-pdn", .data = (ulong)&ufs_config_pdn_clks_data }, - { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_data }, + { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_tree }, + { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_tree }, + { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_tree }, + { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_tree }, + { .compatible = "mediatek,mt8189-ufscfg-ao", .data = (ulong)&ufs_config_ao_clks_tree }, + { .compatible = "mediatek,mt8189-ufscfg-pdn", .data = (ulong)&ufs_config_pdn_clks_tree }, + { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_tree }, { } }; @@ -2034,15 +2028,11 @@ static int mt8189_infrasys_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8189_vlpckgen_clk_tree); } -static int mt8189_clk_gate_probe(struct udevice *dev) +static int mt8189_clk_probe(struct udevice *dev) { - struct mt8189_gate_clk_data *data; - - data = (void *)dev_get_driver_data(dev); + const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev); - return mtk_common_clk_gate_init(dev, &mt8189_clk_tree, - data->gates, data->num_gates, - data->gates[0].id); + return mtk_common_clk_init(dev, tree); } U_BOOT_DRIVER(mt8189_clk_apmixedsys) = { @@ -2082,8 +2072,8 @@ U_BOOT_DRIVER(mt8189_clk_gate) = { .name = "mt8189-gate-clk", .id = UCLASS_CLK, .of_match = of_match_mt8189_clk_gate, - .probe = mt8189_clk_gate_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, + .probe = mt8189_clk_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, .flags = DM_FLAG_PRE_RELOC, }; -- 2.54.0
