Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.

This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <[email protected]>
---
 drivers/clk/mediatek/clk-mt7986.c | 32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7986.c 
b/drivers/clk/mediatek/clk-mt7986.c
index 56e18d403c8..cadb944d551 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -564,10 +564,12 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree 
= {
        .type = MTK_CLK_TREE_INFRASYS,
 };
 
-static const struct mtk_clk_tree mt7986_clk_tree = {
-       .ext_clk_rates = ext_clock_rates,
-       .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
+static int mt7986_clk_probe(struct udevice *dev)
+{
+       const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+       return mtk_common_clk_init(dev, tree);
+}
 
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
        { .compatible = "mediatek,mt7986-fixed-plls" },
@@ -658,11 +660,12 @@ static const struct mtk_gate eth_cgs[] = {
        GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 
15),
 };
 
-static int mt7986_ethsys_probe(struct udevice *dev)
-{
-       return mtk_common_clk_gate_init(dev, &mt7986_clk_tree, eth_cgs,
-                                       ARRAY_SIZE(eth_cgs), 0);
-}
+static const struct mtk_clk_tree mt7986_eth_clk_tree = {
+       .ext_clk_rates = ext_clock_rates,
+       .num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+       .gates = eth_cgs,
+       .num_gates = ARRAY_SIZE(eth_cgs),
+};
 
 static int mt7986_ethsys_bind(struct udevice *dev)
 {
@@ -678,7 +681,10 @@ static int mt7986_ethsys_bind(struct udevice *dev)
 }
 
 static const struct udevice_id mt7986_ethsys_compat[] = {
-       { .compatible = "mediatek,mt7986-ethsys" },
+       {
+               .compatible = "mediatek,mt7986-ethsys",
+               .data = (ulong)&mt7986_eth_clk_tree
+       },
        { }
 };
 
@@ -686,8 +692,8 @@ U_BOOT_DRIVER(mt7986_clk_ethsys) = {
        .name = "mt7986-clock-ethsys",
        .id = UCLASS_CLK,
        .of_match = mt7986_ethsys_compat,
-       .probe = mt7986_ethsys_probe,
+       .probe = mt7986_clk_probe,
        .bind = mt7986_ethsys_bind,
-       .priv_auto = sizeof(struct mtk_cg_priv),
-       .ops = &mtk_clk_gate_ops,
+       .priv_auto = sizeof(struct mtk_clk_priv),
+       .ops = &mtk_clk_topckgen_ops,
 };

-- 
2.54.0

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