The H6 and H616 devicetrees describe the Crypto Engine with module, bus and MBUS clocks plus a bus reset. Add the corresponding gate and reset entries so drivers can enable the CE through the normal clock and reset uclasses in U-Boot proper.
Reviewed-by: Simon Glass <[email protected]> Signed-off-by: James Hilliard <[email protected]> --- Changes v1 -> v2: - Add Simon's Reviewed-by tag --- drivers/clk/sunxi/clk_h6.c | 5 +++++ drivers/clk/sunxi/clk_h616.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 81deb5728e5..27ed5705a14 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -20,6 +20,10 @@ static struct ccu_clk_gate h6_gates[] = { [CLK_DE] = GATE(0x600, BIT(31)), [CLK_BUS_DE] = GATE(0x60c, BIT(0)), + [CLK_CE] = GATE(0x680, BIT(31)), + [CLK_BUS_CE] = GATE(0x68c, BIT(0)), + + [CLK_MBUS_CE] = GATE(0x804, BIT(2)), [CLK_MBUS_NAND] = GATE(0x804, BIT(5)), [CLK_NAND0] = GATE(0x810, BIT(31)), @@ -77,6 +81,7 @@ static struct ccu_clk_gate h6_gates[] = { static struct ccu_reset h6_resets[] = { [RST_BUS_DE] = RESET(0x60c, BIT(16)), + [RST_BUS_CE] = RESET(0x68c, BIT(16)), [RST_BUS_NAND] = RESET(0x82c, BIT(16)), [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c index 3e7eea25bfe..d5b659d0bb2 100644 --- a/drivers/clk/sunxi/clk_h616.c +++ b/drivers/clk/sunxi/clk_h616.c @@ -19,6 +19,10 @@ static struct ccu_clk_gate h616_gates[] = { [CLK_DE] = GATE(0x600, BIT(31)), [CLK_BUS_DE] = GATE(0x60c, BIT(0)), + [CLK_CE] = GATE(0x680, BIT(31)), + [CLK_BUS_CE] = GATE(0x68c, BIT(0)), + + [CLK_MBUS_CE] = GATE(0x804, BIT(2)), [CLK_MBUS_NAND] = GATE(0x804, BIT(5)), [CLK_NAND0] = GATE(0x810, BIT(31)), @@ -86,6 +90,7 @@ static struct ccu_clk_gate h616_gates[] = { static struct ccu_reset h616_resets[] = { [RST_BUS_DE] = RESET(0x60c, BIT(16)), + [RST_BUS_CE] = RESET(0x68c, BIT(16)), [RST_BUS_NAND] = RESET(0x82c, BIT(16)), [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), -- 2.53.0
