Add display related clock drivers, needed for HDMI support. Signed-off-by: Chris-QJ Chen <[email protected]> Signed-off-by: Julien Stephan <[email protected]> --- Add display related clock driver needed for HDMI support that is coming in another series. This series depends on [1], for MediaTek clock driver refactor.
[1]: https://lore.kernel.org/all/20260710-b4-mtk-clk-cleanup-clock-gate-drivers-v1-0-a4b5c491d...@baylibre.com/ --- drivers/clk/mediatek/clk-mt8188.c | 378 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 378 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c index cbaea9f0b2e..4444aafc455 100644 --- a/drivers/clk/mediatek/clk-mt8188.c +++ b/drivers/clk/mediatek/clk-mt8188.c @@ -1687,6 +1687,364 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = { GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6, CLK_TOP_I2C, 1), }; +static const struct mtk_gate_regs vdo0_0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs vdo0_1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +static const struct mtk_gate_regs vdo0_2_cg_regs = { + .set_ofs = 0x124, + .clr_ofs = 0x128, + .sta_ofs = 0x120, +}; + +static const struct mtk_gate_regs vpp0_0_cg_regs = { + .set_ofs = 0x24, + .clr_ofs = 0x28, + .sta_ofs = 0x20, +}; + +static const struct mtk_gate_regs vpp0_1_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x34, + .sta_ofs = 0x2c, +}; + +static const struct mtk_gate_regs vpp0_2_cg_regs = { + .set_ofs = 0x3c, + .clr_ofs = 0x40, + .sta_ofs = 0x38, +}; + +#define GATE_VPP0_0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vpp0_0_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VPP0_1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vpp0_1_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VPP0_2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vpp0_2_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +static const struct mtk_gate vpp0_clks[] = { + /* VPP0_0 */ + GATE_VPP0_0(CLK_VPP0_MDP_FG, CLK_TOP_VPP, 1), + GATE_VPP0_0(CLK_VPP0_STITCH, CLK_TOP_VPP, 2), + GATE_VPP0_0(CLK_VPP0_PADDING, CLK_TOP_VPP, 7), + GATE_VPP0_0(CLK_VPP0_MDP_TCC, CLK_TOP_VPP, 8), + GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, CLK_TOP_VPP, 10), + GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, CLK_TOP_VPP, 11), + GATE_VPP0_0(CLK_VPP0_MUTEX, CLK_TOP_VPP, 13), + GATE_VPP0_0(CLK_VPP02VPP1_RELAY, CLK_TOP_VPP, 14), + GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, CLK_TOP_VPP, 15), + GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, CLK_TOP_VPP, 16), + GATE_VPP0_0(CLK_VPP0_MDP_AAL, CLK_TOP_VPP, 17), + GATE_VPP0_0(CLK_VPP0_MDP_RSZ, CLK_TOP_VPP, 18), + /* VPP0_1 */ + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM, CLK_TOP_VPP, 0), + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM, CLK_TOP_VPP, 1), + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM, CLK_TOP_VPP, 2), + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM, CLK_TOP_VPP, 3), + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM, CLK_TOP_VPP, 4), + GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM, CLK_TOP_VPP, 5), + GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM, CLK_TOP_VPP, 6), + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM, CLK_TOP_VPP, 7), + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM, CLK_TOP_VPP, 8), + GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM, CLK_TOP_VPP, 9), + GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, CLK_TOP_VPP, 10), + GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, CLK_TOP_VPP, 11), + GATE_VPP0_1(CLK_VPP0_MDP_RDMA, CLK_TOP_VPP, 12), + GATE_VPP0_1(CLK_VPP0_MDP_WROT, CLK_TOP_VPP, 13), + GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, CLK_TOP_VPP, 16), + GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, CLK_TOP_VPP, 17), + GATE_VPP0_1(CLK_VPP0_SMI_RSI, CLK_TOP_VPP, 18), + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, CLK_TOP_VPP, 19), + GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, CLK_TOP_VPP, 20), + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, CLK_TOP_VPP, 21), + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, CLK_TOP_VPP, 22), + GATE_VPP0_1(CLK_VPP0_FAKE_ENG, CLK_TOP_VPP, 23), + GATE_VPP0_1(CLK_VPP0_MDP_HDR, CLK_TOP_VPP, 24), + GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, CLK_TOP_VPP, 25), + GATE_VPP0_1(CLK_VPP0_MDP_COLOR, CLK_TOP_VPP, 26), + GATE_VPP0_1(CLK_VPP0_MDP_OVL, CLK_TOP_VPP, 27), + GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, CLK_TOP_VPP, 28), + GATE_VPP0_1(CLK_VPP0_DISP_WDMA, CLK_TOP_VPP, 29), + GATE_VPP0_1(CLK_VPP0_MDP_HMS, CLK_TOP_VPP, 30), + /* VPP0_2 */ + GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, CLK_TOP_WPE_VPP, 0), + GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, CLK_TOP_WPE_VPP, 1), + GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, CLK_TOP_WPE_VPP, 2), + GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, CLK_TOP_WPE_VPP, 3), +}; + +static const struct mtk_gate_regs vpp1_0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs vpp1_1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_VPP1_0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vpp1_0_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VPP1_1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vpp1_1_cg_regs, _shift,\ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +static const struct mtk_gate vpp1_clks[] = { + /* VPP1_0 */ + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, CLK_TOP_VPP, 0), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, CLK_TOP_VPP, 1), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, CLK_TOP_VPP, 2), + GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, CLK_TOP_VPP, 3), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, CLK_TOP_VPP, 4), + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, CLK_TOP_VPP, 5), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, CLK_TOP_VPP, 6), + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, CLK_TOP_VPP, 7), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, CLK_TOP_VPP, 8), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, CLK_TOP_VPP, 9), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, CLK_TOP_VPP, 10), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, CLK_TOP_VPP, 11), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, CLK_TOP_VPP, 12), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, CLK_TOP_VPP, 13), + GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, CLK_TOP_VPP, 14), + GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, CLK_TOP_VPP, 15), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, CLK_TOP_VPP, 16), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, CLK_TOP_VPP, 17), + GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, CLK_TOP_VPP, 18), + GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, CLK_TOP_VPP, 19), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, CLK_TOP_VPP, 20), + GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, CLK_TOP_VPP, 21), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, CLK_TOP_VPP, 22), + GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, CLK_TOP_VPP, 23), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, CLK_TOP_VPP, 24), + GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, CLK_TOP_VPP, 25), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, CLK_TOP_VPP, 26), + GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, CLK_TOP_VPP, 27), + GATE_VPP1_0(CLK_VPP1_GALS5, CLK_TOP_VPP, 28), + GATE_VPP1_0(CLK_VPP1_GALS6, CLK_TOP_VPP, 29), + GATE_VPP1_0(CLK_VPP1_LARB5, CLK_TOP_VPP, 30), + GATE_VPP1_0(CLK_VPP1_LARB6, CLK_TOP_VPP, 31), + /* VPP1_1 */ + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, CLK_TOP_VPP, 0), + GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, CLK_TOP_VPP, 1), + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, CLK_TOP_VPP, 2), + GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, CLK_TOP_VPP, 3), + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, CLK_TOP_VPP, 4), + GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, CLK_TOP_VPP, 5), + GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, CLK_TOP_VPP, 7), + GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, CLK_TOP_VPP, 8), + GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, CLK_TOP_VPP, 9), + GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, CLK_TOP_VPP, 10), + GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, CLK_TOP_VPP, 11), + GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, CLK_TOP_VPP, 12), + GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, CLK_TOP_VPP, 13), + GATE_VPP1_1(CLK_VPP1_HDMI_META, CLK_TOP_VPP, 16), + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, CLK_TOP_VPP, 17), + GATE_VPP1_1(CLK_VPP1_DGI_IN, CLK_TOP_VPP, 18), + GATE_VPP1_1(CLK_VPP1_DGI_OUT, CLK_TOP_VPP, 19), + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, CLK_TOP_VPP, 20), + GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, CLK_TOP_VPP, 21), + GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, CLK_TOP_VPP, 26), +}; + +#define GATE_VDO0_0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo0_0_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO0_1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo0_1_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO0_2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo0_2_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +static const struct mtk_gate vdo0_clks[] = { + /* VDO0_0 */ + GATE_VDO0_0(CLK_VDO0_DISP_OVL0, CLK_TOP_VPP, 0), + GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, CLK_TOP_VPP, 2), + GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, CLK_TOP_VPP, 4), + GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, CLK_TOP_VPP, 6), + GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, CLK_TOP_VPP, 8), + GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, CLK_TOP_VPP, 10), + GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, CLK_TOP_VPP, 17), + GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, CLK_TOP_VPP, 19), + GATE_VDO0_0(CLK_VDO0_DSI0, CLK_TOP_VPP, 21), + GATE_VDO0_0(CLK_VDO0_DSI1, CLK_TOP_VPP, 22), + GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, CLK_TOP_VPP, 23), + GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, CLK_TOP_VPP, 24), + GATE_VDO0_0(CLK_VDO0_DP_INTF0, CLK_TOP_VPP, 25), + GATE_VDO0_0(CLK_VDO0_DISP_AAL0, CLK_TOP_VPP, 26), + GATE_VDO0_0(CLK_VDO0_INLINEROT0, CLK_TOP_VPP, 27), + GATE_VDO0_0(CLK_VDO0_APB_BUS, CLK_TOP_VPP, 28), + GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, CLK_TOP_VPP, 29), + GATE_VDO0_0(CLK_VDO0_MDP_WROT0, CLK_TOP_VPP, 30), + GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, CLK_TOP_VPP, 31), + /* VDO0_1 */ + GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, CLK_TOP_VPP, 0), + GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, CLK_TOP_VPP, 1), + GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, CLK_TOP_VPP, 5), + GATE_VDO0_1(CLK_VDO0_DL_RELAY3, CLK_TOP_VPP, 6), + GATE_VDO0_1(CLK_VDO0_DL_RELAY4, CLK_TOP_VPP, 7), + GATE_VDO0_1(CLK_VDO0_SMI_GALS, CLK_TOP_VPP, 10), + GATE_VDO0_1(CLK_VDO0_SMI_COMMON, CLK_TOP_VPP, 11), + GATE_VDO0_1(CLK_VDO0_SMI_EMI, CLK_TOP_VPP, 12), + GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, CLK_TOP_VPP, 13), + GATE_VDO0_1(CLK_VDO0_SMI_LARB, CLK_TOP_VPP, 14), + GATE_VDO0_1(CLK_VDO0_SMI_RSI, CLK_TOP_VPP, 15), + /* VDO0_2 */ + GATE_VDO0_2(CLK_VDO0_DSI0_DSI, CLK_TOP_DSI_OCC, 0), + GATE_VDO0_2(CLK_VDO0_DSI1_DSI, CLK_TOP_DSI_OCC, 8), + GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, CLK_TOP_EDP, 16), +}; + +static const struct mtk_gate_regs vdo1_0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs vdo1_1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +static const struct mtk_gate_regs vdo1_2_cg_regs = { + .set_ofs = 0x124, + .clr_ofs = 0x128, + .sta_ofs = 0x120, +}; + +static const struct mtk_gate_regs vdo1_3_cg_regs = { + .set_ofs = 0x134, + .clr_ofs = 0x138, + .sta_ofs = 0x130, +}; + +static const struct mtk_gate_regs vdo1_4_cg_regs = { + .set_ofs = 0x144, + .clr_ofs = 0x148, + .sta_ofs = 0x140, +}; + +static const struct mtk_gate_regs vdo1_5_cg_regs = { + .set_ofs = 0x400, + .clr_ofs = 0x400, + .sta_ofs = 0x400, +}; + +#define GATE_VDO1_0(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo1_0_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO1_1(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo1_1_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO1_2(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo1_2_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO1_3(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo1_3_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO1_4(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo1_4_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +#define GATE_VDO1_5(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &vdo1_5_cg_regs, _shift, \ + CLK_PARENT_TOPCKGEN | CLK_GATE_SETCLR) + +static const struct mtk_gate vdo1_clks[] = { + /* VDO1_0 */ + GATE_VDO1_0(CLK_VDO1_SMI_LARB2, CLK_TOP_VPP, 0), + GATE_VDO1_0(CLK_VDO1_SMI_LARB3, CLK_TOP_VPP, 1), + GATE_VDO1_0(CLK_VDO1_GALS, CLK_TOP_VPP, 2), + GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, CLK_TOP_VPP, 3), + GATE_VDO1_0(CLK_VDO1_FAKE_ENG1, CLK_TOP_VPP, 4), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, CLK_TOP_VPP, 5), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, CLK_TOP_VPP, 6), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, CLK_TOP_VPP, 7), + GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, CLK_TOP_VPP, 8), + GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, CLK_TOP_VPP, 9), + GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, CLK_TOP_VPP, 10), + GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, CLK_TOP_VPP, 11), + /* VDO1_1 */ + GATE_VDO1_1(CLK_VDO1_VPP_MERGE3, CLK_TOP_VPP, 0), + GATE_VDO1_1(CLK_VDO1_VPP_MERGE4, CLK_TOP_VPP, 1), + GATE_VDO1_1(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, CLK_TOP_VPP, 2), + GATE_VDO1_1(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, CLK_TOP_VPP, 3), + GATE_VDO1_1(CLK_VDO1_DISP_MUTEX, CLK_TOP_VPP, 4), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA4, CLK_TOP_VPP, 5), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA5, CLK_TOP_VPP, 6), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA6, CLK_TOP_VPP, 7), + GATE_VDO1_1(CLK_VDO1_MDP_RDMA7, CLK_TOP_VPP, 8), + GATE_VDO1_1(CLK_VDO1_DP_INTF0_MMCK, CLK_TOP_VPP, 9), + GATE_VDO1_1(CLK_VDO1_DPI0_MM, CLK_TOP_VPP, 10), + GATE_VDO1_1(CLK_VDO1_DPI1_MM, CLK_TOP_VPP, 11), + GATE_VDO1_1(CLK_VDO1_MERGE0_DL_ASYNC, CLK_TOP_VPP, 13), + GATE_VDO1_1(CLK_VDO1_MERGE1_DL_ASYNC, CLK_TOP_VPP, 14), + GATE_VDO1_1(CLK_VDO1_MERGE2_DL_ASYNC, CLK_TOP_VPP, 15), + GATE_VDO1_1(CLK_VDO1_MERGE3_DL_ASYNC, CLK_TOP_VPP, 16), + GATE_VDO1_1(CLK_VDO1_MERGE4_DL_ASYNC, CLK_TOP_VPP, 17), + GATE_VDO1_1(CLK_VDO1_DSC_VDO1_DL_ASYNC, CLK_TOP_VPP, 18), + GATE_VDO1_1(CLK_VDO1_MERGE_VDO1_DL_ASYNC, CLK_TOP_VPP, 19), + GATE_VDO1_1(CLK_VDO1_PADDING0, CLK_TOP_VPP, 20), + GATE_VDO1_1(CLK_VDO1_PADDING1, CLK_TOP_VPP, 21), + GATE_VDO1_1(CLK_VDO1_PADDING2, CLK_TOP_VPP, 22), + GATE_VDO1_1(CLK_VDO1_PADDING3, CLK_TOP_VPP, 23), + GATE_VDO1_1(CLK_VDO1_PADDING4, CLK_TOP_VPP, 24), + GATE_VDO1_1(CLK_VDO1_PADDING5, CLK_TOP_VPP, 25), + GATE_VDO1_1(CLK_VDO1_PADDING6, CLK_TOP_VPP, 26), + GATE_VDO1_1(CLK_VDO1_PADDING7, CLK_TOP_VPP, 27), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ0, CLK_TOP_VPP, 28), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ1, CLK_TOP_VPP, 29), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ2, CLK_TOP_VPP, 30), + GATE_VDO1_1(CLK_VDO1_DISP_RSZ3, CLK_TOP_VPP, 31), + /* VDO1_2 */ + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0, CLK_TOP_VPP, 0), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0, CLK_TOP_VPP, 1), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE, CLK_TOP_VPP, 2), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1, CLK_TOP_VPP, 16), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1, CLK_TOP_VPP, 17), + GATE_VDO1_2(CLK_VDO1_DISP_MIXER, CLK_TOP_VPP, 18), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, CLK_TOP_VPP, 19), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, CLK_TOP_VPP, 20), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, CLK_TOP_VPP, 21), + GATE_VDO1_2(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, CLK_TOP_VPP, 22), + GATE_VDO1_2(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, CLK_TOP_VPP, 23), + /* VDO1_3 */ + GATE_VDO1_3(CLK_VDO1_DPI0, CLK_TOP_VPP, 0), + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI0, CLK_TOP_VPP, 1), + GATE_VDO1_3(CLK_VDO1_DPI1, CLK_TOP_VPP, 8), + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPI1, CLK_TOP_VPP, 9), + GATE_VDO1_3(CLK_VDO1_DPINTF, CLK_TOP_VPP, 16), + GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, CLK_TOP_VPP, 17), + /* VDO1_4 */ + GATE_VDO1_4(CLK_VDO1_26M_SLOW, CLK_PAD_CLK26M, 8), + /* VDO1_5 */ + GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, CLK_TOP_VPP, 0), +}; + static const struct mtk_clk_tree mt8188_clk_tree = { .ext_clk_rates = ext_clock_rates, .num_ext_clks = ARRAY_SIZE(ext_clock_rates), @@ -1697,6 +2055,10 @@ MTK_GATE_CLK_DATA(pericfg_ao_clks); MTK_GATE_CLK_DATA(imp_iic_wrap_c_clks); MTK_GATE_CLK_DATA(imp_iic_wrap_w_clks); MTK_GATE_CLK_DATA(imp_iic_wrap_en_clks); +MTK_GATE_CLK_DATA(vpp0_clks); +MTK_GATE_CLK_DATA(vpp1_clks); +MTK_GATE_CLK_DATA(vdo0_clks); +MTK_GATE_CLK_DATA(vdo1_clks); static const struct udevice_id of_match_mt8188_clk_gate[] = { { @@ -1719,6 +2081,22 @@ static const struct udevice_id of_match_mt8188_clk_gate[] = { .compatible = "mediatek,mt8188-imp-iic-wrap-en", .data = (ulong)&imp_iic_wrap_en_clks_data }, + { + .compatible = "mediatek,mt8188-vppsys0", + .data = (ulong)&vpp0_clks_data + }, + { + .compatible = "mediatek,mt8188-vppsys1", + .data = (ulong)&vpp1_clks_data + }, + { + .compatible = "mediatek,mt8188-vdosys0", + .data = (ulong)&vdo0_clks_data + }, + { + .compatible = "mediatek,mt8188-vdosys1", + .data = (ulong)&vdo1_clks_data + }, { } }; --- base-commit: b5fca5f601e5da4955a3ab815f614e1a1300ec2b change-id: 20260710-mt8188-add-clk-add-display-related-clocks-02b34af99fd8 prerequisite-message-id: 20260710-b4-mtk-clk-cleanup-clock-gate-drivers-v1-0-a4b5c491d...@baylibre.com prerequisite-patch-id: 68c5aa18eb36d10d12334abef330b86144eaed7a prerequisite-patch-id: 853ec3fbe33d04e38871f5f156b90a1d1a4cb09f prerequisite-patch-id: 7fe98e35927153e3e19744492104107aaec498a5 prerequisite-patch-id: 49d38765dc53011d25a98f041ce93d6dce251b77 prerequisite-patch-id: 48eeae79a82161dcda5b59bb07d940709a55ab6f prerequisite-patch-id: 9af855a2db85b152e48d888d412cd3fbd75b0f9a prerequisite-patch-id: a6efe0d0069974bbb5c9cf0d7a076faa3f7e13bb prerequisite-patch-id: dc7618afdc12543fbaafd1562abd2deafeeea576 prerequisite-patch-id: fbf72c0f0314129e23334d2faa8187808285232e Best regards, -- Julien Stephan <[email protected]>
