Add clock tree type flags to the mt7987 clock tree structures. These will be used later for parent lookup.
Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mt7987.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 5f102636079..b455f52bafc 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -60,6 +60,7 @@ static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, + .type = MTK_CLK_TREE_APMIXED, }; static const struct udevice_id mt7987_fixed_pll_compat[] = { @@ -457,6 +458,12 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), .flags = CLK_PARENT_TOPCKGEN, + .type = MTK_CLK_TREE_TOPCKGEN, +}; + +static const struct mtk_clk_tree mt7987_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct udevice_id mt7987_topckgen_compat[] = { @@ -783,6 +790,7 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), + .type = MTK_CLK_TREE_INFRASYS, }; static const struct udevice_id mt7987_infracfg_compat[] = { @@ -829,7 +837,7 @@ static const struct mtk_gate eth_cgs[] = { static int mt7987_ethsys_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, eth_cgs, + return mtk_common_clk_gate_init(dev, &mt7987_clk_tree, eth_cgs, ARRAY_SIZE(eth_cgs), 0); } -- 2.43.0
