Add PCIe controller, PHY and root port device tree nodes for K1 SoC on Banana Pi F3 and MusePi Pro boards. Enable the PCIe driver and NVMe support in spacemit_k1_defconfig.
Signed-off-by: Eric Chung <[email protected]> --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 151 +++++++++++++++++++++++++++++ arch/riscv/dts/k1-musepi-pro-u-boot.dtsi | 153 ++++++++++++++++++++++++++++++ configs/spacemit_k1_defconfig | 8 ++ 3 files changed, 312 insertions(+) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index 582bd61d27c..d9370c58650 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2026 RISCstar Ltd. */ +#include <dt-bindings/phy/phy.h> #include "binman.dtsi" / { @@ -98,6 +99,123 @@ / { soc { + pcie-bus { + pcie0: pcie@ca000000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "link"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; + interrupts = <141>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "dbi", "mstr", "slv"; + resets = <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "dbi", "mstr", "slv"; + spacemit,apmu = <&syscon_apmu 0x03cc>; + phys = <&combo_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + status = "disabled"; + + pcie0_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1: pcie@ca400000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "link"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; + interrupts = <142>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names = "dbi", "mstr", "slv"; + resets = <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names = "dbi", "mstr", "slv"; + spacemit,apmu = <&syscon_apmu 0x03d4>; + phys = <&pcie1_phy>; + phy-names = "pcie-phy"; + + pcie1_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie2: pcie@ca800000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "link"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, + <0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x17000000>; + interrupts = <143>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names = "dbi", "mstr", "slv"; + resets = <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>; + reset-names = "dbi", "mstr", "slv"; + spacemit,apmu = <&syscon_apmu 0x03dc>; + phys = <&pcie2_phy>; + phy-names = "pcie-phy"; + + pcie2_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; + storage-bus { sdhci0: mmc@d4280000 { bootph-pre-ram; @@ -172,6 +290,39 @@ vmmc-supply = <&buck4_3v3>; }; +&combo_phy { + status = "okay"; +}; + +&pcie1_phy { + /* + * pinctrl must stay disabled on PHY nodes: the default pcie1_3_cfg + * removes the pull-up on CLKREQ# (open-drain), leaving it floating + * when the endpoint does not actively drive it low. Without a valid + * CLKREQ# the controller will not complete link training. + */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie2_phy { + /* + * pinctrl must stay disabled on PHY nodes (see pcie1_phy above). + */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; +}; + +&pcie2_port { + phys = <&pcie2_phy>; +}; + &binman { u-boot-spl-ddr { type = "section"; diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi index ac67db13d7b..20fe71cdc40 100644 --- a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi +++ b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/clock/spacemit,k1-syscon.h> +#include <dt-bindings/phy/phy.h> #include "binman.dtsi" / { @@ -253,6 +254,125 @@ / { soc { + pcie-bus { + pcie0: pcie@ca000000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "link"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; + interrupts = <141>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "dbi", "mstr", "slv"; + resets = <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "dbi", "mstr", "slv"; + spacemit,apmu = <&syscon_apmu 0x03cc>; + phys = <&combo_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + status = "disabled"; + + pcie0_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1: pcie@ca400000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "link"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; + interrupts = <142>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names = "dbi", "mstr", "slv"; + resets = <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names = "dbi", "mstr", "slv"; + spacemit,apmu = <&syscon_apmu 0x03d4>; + phys = <&pcie1_phy>; + phy-names = "pcie-phy"; + status = "okay"; + + pcie1_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie2: pcie@ca800000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "link"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, + <0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x17000000>; + interrupts = <143>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names = "dbi", "mstr", "slv"; + resets = <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>; + reset-names = "dbi", "mstr", "slv"; + spacemit,apmu = <&syscon_apmu 0x03dc>; + phys = <&pcie2_phy>; + phy-names = "pcie-phy"; + status = "okay"; + + pcie2_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; + storage-bus { sdhci0: mmc@d4280000 { bootph-pre-ram; @@ -327,6 +447,39 @@ vmmc-supply = <&buck4_3v3>; }; +&combo_phy { + status = "okay"; +}; + +&pcie1_phy { + /* + * pinctrl must stay disabled on PHY nodes: the default pcie1_3_cfg + * removes the pull-up on CLKREQ# (open-drain), leaving it floating + * when the endpoint does not actively drive it low. Without a valid + * CLKREQ# the controller will not complete link training. + */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie2_phy { + /* + * pinctrl must stay disabled on PHY nodes (see pcie1_phy above). + */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; +}; + +&pcie2_port { + phys = <&pcie2_phy>; +}; + &binman { u-boot-spl-ddr { type = "section"; diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index 1c92c4082a7..08f207c09bc 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -108,6 +108,14 @@ CONFIG_CMD_MMC=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMINFO_MAP=y CONFIG_EFI_PARTITION=y +CONFIG_PCI=y +CONFIG_CMD_PCI=y +CONFIG_NVME=y +CONFIG_NVME_PCI=y +CONFIG_CMD_NVME=y +CONFIG_PCIE_DW_SPACEMIT=y +CONFIG_PHY=y +CONFIG_PHY_SPACEMIT_K1_PCIE=y CONFIG_SPL_SPI=y CONFIG_SPL_DM_SPI=y CONFIG_SPL_DM_SPI_FLASH=y -- 2.51.0
