From: Dinesh Maniyam <[email protected]> Add the Arria 10 SoCDK QSPI and NAND board variants.
Each board ships with a minimal top-level device tree under arch/arm/dts that includes the existing socfpga_arria10_socdk.dtsi and enables the relevant storage peripheral: - arch/arm/dts/socfpga_arria10_socdk_nand.dts enables the Denali NAND controller and declares two MTD partitions (boot/FPGA data and the JFFS2 rootfs). - arch/arm/dts/socfpga_arria10_socdk_qspi.dts enables the Cadence QSPI controller. The matching defconfigs select the new device trees, the storage-specific drivers (NAND_DENALI_DT + SPL_NAND_CADENCE for NAND; Cadence QSPI for QSPI), and the SPL memory layout shared with the existing SDMMC variant. Board-specific run-time settings live in include/configs/socfpga_arria10_socdk.h. The boards do not use CONFIG_OF_UPSTREAM because the upstream Linux Arria 10 device tree does not provide the clkmgr (and related) labels that arch/arm/dts/socfpga_arria10-u-boot.dtsi references; the in-tree arch/arm/dts copy continues to provide those labels for U-Boot. Signed-off-by: Dinesh Maniyam <[email protected]> --- arch/arm/dts/socfpga_arria10_socdk_nand.dts | 26 ++++++ arch/arm/dts/socfpga_arria10_socdk_qspi.dts | 11 +++ configs/socfpga_arria10_nand_defconfig | 95 +++++++++++++++++++++ configs/socfpga_arria10_qspi_defconfig | 86 +++++++++++++++++++ include/configs/socfpga_arria10_socdk.h | 27 ++++++ 5 files changed, 245 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_socdk_nand.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi.dts create mode 100644 configs/socfpga_arria10_nand_defconfig create mode 100644 configs/socfpga_arria10_qspi_defconfig diff --git a/arch/arm/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/dts/socfpga_arria10_socdk_nand.dts new file mode 100644 index 00000000000..07e6c6a788b --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_nand.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015-2022 Altera Corporation. All rights reserved. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&nand { + status = "okay"; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x02500000>; + }; + partition@1c00000 { + label = "Root Filesystem - JFFS2"; + reg = <0x02500000 0x05500000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 00000000000..3128a11ba1d --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Intel Corporation. All rights reserved. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&qspi { + status = "okay"; +}; diff --git a/configs/socfpga_arria10_nand_defconfig b/configs/socfpga_arria10_nand_defconfig new file mode 100644 index 00000000000..2b9b776baff --- /dev/null +++ b/configs/socfpga_arria10_nand_defconfig @@ -0,0 +1,95 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x200000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_nand" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0xffe2b000 +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y +CONFIG_ENV_OFFSET_REDUND=0x210000 +CONFIG_IDENT_STRING="socfpga_arria10" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x0 +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 " +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="bridge enable; run nandload; run nandboot" +CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_nand.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x15000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FPGA=y +CONFIG_SPL_MTD=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb80000.nand.0" +CONFIG_OF_LIST="" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_REDUNDANT=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DWAPB_GPIO=y +CONFIG_MISC=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +# CONFIG_MMC is not set +CONFIG_DM_MTD=y +CONFIG_NAND_DENALI_DT=y +CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_PAGE_SIZE=0x800 +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000 +CONFIG_SPL_NAND_CADENCE=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/configs/socfpga_arria10_qspi_defconfig b/configs/socfpga_arria10_qspi_defconfig new file mode 100644 index 00000000000..2ede110eb25 --- /dev/null +++ b/configs/socfpga_arria10_qspi_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x200000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_qspi" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0xffe2b000 +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y +CONFIG_ENV_OFFSET_REDUND=0x210000 +CONFIG_IDENT_STRING="socfpga_arria10" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x0 +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 " +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="bridge enable; run qspiload; run qspiboot" +CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_qspi.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_PAD_TO=0x40000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x15000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FPGA=y +CONFIG_SPL_MTD=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_OF_LIST="" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_REDUNDANT=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DWAPB_GPIO=y +CONFIG_MISC=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +# CONFIG_MMC is not set +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 35c777b774e..8ca8ba7be51 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -32,6 +32,33 @@ /* SPL memory allocation configuration, this is for FAT implementation */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_NAND_BOOT) +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0xa000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdt_addr_r=0x02000000\0" \ + "scriptaddr=0x02100000\0" \ + "pxefile_addr_r=0x02200000\0" \ + "ramdisk_addr_r=0x02300000\0" \ + "socfpga_legacy_reset_compat=1\0" \ + "kernelfit_addr=0x1200000\0" \ + "fitimagesize=0x5F0000\0" \ + "qspiroot=/dev/mtdblock1\0" \ + "qspirootfstype=jffs2\0" \ + "qspiload=sf probe; sf read ${scriptaddr} ${kernelfit_addr}\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + "root=${qspiroot} rw rootfstype=${qspirootfstype}; " \ + "bootm ${scriptaddr}\0" \ + "nandroot=/dev/mtdblock1\0" \ + "nandrootfstype=jffs2\0" \ + "nandload=nand read ${scriptaddr} ${kernelfit_addr}\0" \ + "nandboot=setenv bootargs " CONFIG_BOOTARGS \ + "root=${nandroot} rw rootfstype=${nandrootfstype}; " \ + "bootm ${scriptaddr}\0" \ + +#endif + /* The rest of the configuration is shared */ #include <configs/socfpga_common.h> -- 2.43.7
