From: Dinesh Maniyam <[email protected]> Introduce a separate DTS for NAND2 boot flow where MMC is not enabled. This ensures that only NAND configures the ComboPHY, avoiding conflicts caused by DT not matching handoff ownership.
Signed-off-by: Dinesh Maniyam <[email protected]> --- arch/arm/dts/Makefile | 1 + .../socfpga_agilex5_socdk_nand2-u-boot.dtsi | 180 ++++++++++++++++++ arch/arm/dts/socfpga_agilex5_socdk_nand2.dts | 10 + configs/socfpga_agilex5_nand2_defconfig | 2 +- 4 files changed, 192 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_nand2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_nand2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2b65cd9105c..3a523f18239 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -428,6 +428,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_emmc.dtb \ + socfpga_agilex5_socdk_nand2.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_2.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5_socdk_nand2-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk_nand2-u-boot.dtsi new file mode 100644 index 00000000000..4bfa01458bc --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_nand2-u-boot.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions for Agilex5 SocDK NAND2 + * + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + * + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + * + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; + */ + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &flash0,&nand,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { + status = "disabled"; + bootph-all; +}; + +&qspi { + status = "okay"; +}; + +&nand { + status = "okay"; + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "disabled"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +#if defined(CONFIG_FIT) && !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&binman { + /delete-node/ kernel; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex5_socdk_nand2.dts b/arch/arm/dts/socfpga_agilex5_socdk_nand2.dts new file mode 100644 index 00000000000..0266a2f5c5a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_nand2.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5_socdk.dts" + +&mmc { + status = "disabled"; +}; diff --git a/configs/socfpga_agilex5_nand2_defconfig b/configs/socfpga_agilex5_nand2_defconfig index c9c7077be91..a6a8c34c9b1 100644 --- a/configs/socfpga_agilex5_nand2_defconfig +++ b/configs/socfpga_agilex5_nand2_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_nand2" CONFIG_BOOTARGS="earlycon panic=-1 root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1" CONFIG_TARGET_SOCFPGA_AGILEX5_NAND2=y CONFIG_PHY_CADENCE_COMBOPHY=n -- 2.43.7
