Deasserting DDR retention pin is quite similar from J7200, J784s4, J721e, and j721s2 SoCs.
Instead of duplicating almost the same code, add it in lpm-common.c. NB: On J7200, there's a latch, so the clock needs to be toggled. Signed-off-by: Richard Genoud (TI) <[email protected]> --- arch/arm/mach-k3/lpm-common.h | 2 ++ arch/arm/mach-k3/r5/lpm-common.c | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/mach-k3/lpm-common.h b/arch/arm/mach-k3/lpm-common.h index 2b360e6f03f3..2e3ea4428124 100644 --- a/arch/arm/mach-k3/lpm-common.h +++ b/arch/arm/mach-k3/lpm-common.h @@ -11,5 +11,7 @@ void __noreturn do_resume(void); void lpm_process(void); +void k3_deassert_ddr_ret(const char *pmic_name, unsigned int ddr_ret_val, + unsigned int ddr_ret_clk, bool toggle); #endif diff --git a/arch/arm/mach-k3/r5/lpm-common.c b/arch/arm/mach-k3/r5/lpm-common.c index 95f777c5029f..afc6b5cf5376 100644 --- a/arch/arm/mach-k3/r5/lpm-common.c +++ b/arch/arm/mach-k3/r5/lpm-common.c @@ -41,6 +41,33 @@ struct lpm_addr_info { /* This is used by J722s */ __weak void ctrl_mmr_unlock(void) { } +#define GPIO_OUT_1 0x3D +void k3_deassert_ddr_ret(const char *pmic_name, unsigned int ddr_ret_val, + unsigned int ddr_ret_clk, bool toggle) +{ + struct udevice *pmic; + int regval; + int err; + + err = uclass_get_device_by_name(UCLASS_PMIC, pmic_name, &pmic); + if (err) { + printf("Getting %s init failed: %d\n", pmic_name, err); + return; + } + + /* Set DDR_RET Signal Low on PMIC */ + regval = pmic_reg_read(pmic, GPIO_OUT_1) & ~ddr_ret_val; + pmic_reg_write(pmic, GPIO_OUT_1, regval); + + if (toggle) { + /* Now toggle the CLK of the latch for DDR retention */ + pmic_reg_write(pmic, GPIO_OUT_1, regval | ddr_ret_clk); + pmic_reg_write(pmic, GPIO_OUT_1, regval & ~ddr_ret_clk); + pmic_reg_write(pmic, GPIO_OUT_1, regval | ddr_ret_clk); + pmic_reg_write(pmic, GPIO_OUT_1, regval & ~ddr_ret_clk); + } +} + /* in board_init_f(), there's no BSS, so we can't use global/static variables */ bool j7xx_board_is_resuming(void) {
