On Fri, 2026-06-12 at 07:57 +0000, [email protected] wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > Hi, > > > > > All currently supported ESMT/EON flashes supports 4KB sector and > > dual/quad > > read. > > > > Link: > > https://urldefense.com/v3/__https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B.pdf__;!!CTRNKA9wMg0ARbw!loGGxfD6Cz6vPt1rShQD1VK39EnUqHA4wA-sj11XPNLZYHslG0iY9ti_X1WIobvc_XTx610jrDxeE7ApjOUpZuZlSKdjMqk$ > > Link: > > https://urldefense.com/v3/__https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QH128A*20(2TC).pdf__;JQ!!CTRNKA9wMg0ARbw!loGGxfD6Cz6vPt1rShQD1VK39EnUqHA4wA-sj11XPNLZYHslG0iY9ti_X1WIobvc_XTx610jrDxeE7ApjOUpZuZlftRl0h8$ > > Link: > > https://urldefense.com/v3/__https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25S64A(2SC).pdf__;!!CTRNKA9wMg0ARbw!loGGxfD6Cz6vPt1rShQD1VK39EnUqHA4wA-sj11XPNLZYHslG0iY9ti_X1WIobvc_XTx610jrDxeE7ApjOUpZuZl8G8RB38$ > > Signed-off-by: Weijie Gao <[email protected]> > > --- > > v5: not changed > > v3-v4: updated commit message > > v2: not changed > > --- > > drivers/mtd/spi/spi-nor-ids.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi- > > nor-ids.c > > index c0fa98424aa..7d96adab4fd 100644 > > --- a/drivers/mtd/spi/spi-nor-ids.c > > +++ b/drivers/mtd/spi/spi-nor-ids.c > > @@ -90,12 +90,12 @@ const struct flash_info spi_nor_ids[] = { > > #endif > > #ifdef CONFIG_SPI_FLASH_EON /* EON */ > > /* EON -- en25xxx */ > > - { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) > > }, > > - { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, > > - { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) > > }, > > - { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, > > - { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, > > - { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) > > }, > > + { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K > > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > + { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, SECT_4K > > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > + { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K > > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, SECT_4K > > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > + { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K > > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > + { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K > > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > If SPI_NOR_QUAD_READ is given, the driver assumes the chip supports > Quad Output Read (1-1-4, 6Bh) and Quad Page Program (1-1-4, 32h). > Except en25qh128, those chips don't support 1-1-4 read/program per > datasheets. > They do support Quad I/O Read (1-4-4, EBh). If you want to enable it, > write fixup otherwise just drop the SPI_NOR_QUAD_READ flag, please. >
This is my mistake. I bought one en25qh128 to test and confirmed that. I'll drop all incompatible quad read flags. > Thanks, > Takahiro >
