The mach_cpu_init() function is not invoked in SPL. Instead of
having two functions, fold mach_cpu_init() into board_init_f(),
which is called very early in the boot process and assures that
the CPG and APMU setup will be invoked before DM is brought up.
Fixes: 37997a214ed1 ("arm: renesas: Use stock lowlevel_init function and remove
s_init")
Signed-off-by: Marek Vasut <[email protected]>
---
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: [email protected]
---
board/renesas/common/gen4-spl.c | 41 +++++++++++++++------------------
1 file changed, 18 insertions(+), 23 deletions(-)
diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c
index e4c1190eac7..5a0b0ebe115 100644
--- a/board/renesas/common/gen4-spl.c
+++ b/board/renesas/common/gen4-spl.c
@@ -18,6 +18,12 @@
#include <mapmem.h>
#include <spl.h>
+#define APMU_BASE 0xe6170000U
+#define CL0GRP3_BIT BIT(3)
+#define CL1GRP3_BIT BIT(7)
+#define RTGRP3_BIT BIT(19)
+#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
+
#define CNTCR_EN BIT(0)
#ifdef CONFIG_SPL_BUILD
@@ -47,6 +53,18 @@ void board_init_f(ulong dummy)
struct udevice *dev;
int ret;
+ /* Unlock CPG access */
+ writel(0x5A5AFFFF, CPGWPR);
+ writel(0xA5A50000, CPGWPCR);
+ init_generic_timer();
+
+ /* Define for Work Around of APMU */
+ writel(0x00ff00ff, APMU_BASE + 0x10);
+ writel(0x00ff00ff, APMU_BASE + 0x14);
+ writel(0x00ff00ff, APMU_BASE + 0x18);
+ writel(0x00ff00ff, APMU_BASE + 0x1c);
+ clrbits_le32(APMU_BASE + 0x68, BIT(29));
+
if (CONFIG_IS_ENABLED(OF_CONTROL)) {
ret = spl_early_init();
if (ret) {
@@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset,
size_t size)
return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0);
}
-#define APMU_BASE 0xe6170000U
-#define CL0GRP3_BIT BIT(3)
-#define CL1GRP3_BIT BIT(7)
-#define RTGRP3_BIT BIT(19)
-#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT)
-
-int mach_cpu_init(void)
-{
- /* Unlock CPG access */
- writel(0x5A5AFFFF, CPGWPR);
- writel(0xA5A50000, CPGWPCR);
- init_generic_timer();
-
- /* Define for Work Around of APMU */
- writel(0x00ff00ff, APMU_BASE + 0x10);
- writel(0x00ff00ff, APMU_BASE + 0x14);
- writel(0x00ff00ff, APMU_BASE + 0x18);
- writel(0x00ff00ff, APMU_BASE + 0x1c);
- clrbits_le32(APMU_BASE + 0x68, BIT(29));
-
- return 0;
-}
-
void reset_cpu(void)
{
}
--
2.53.0
