Add nor_early_init() to probe the QSPI controller and SPI NOR flash in SPL. Switch spl_boot_device() to BOOT_DEVICE_SPI so the board boots from SPI flash.
Change the default device tree to k1-musepi-pro, whose u-boot overlay already defines the QSPI controller and flash node with bootph-pre-ram markers. Enable the required SPI driver model and flash config options. Signed-off-by: Guodong Xu <[email protected]> --- v2: - Renamed and reworked from v1 11/16 "board: k1: enable SPI NOR flash in SPL". - New k1-musepi-pro-u-boot.dtsi overlay; default DT switched to it. - SPL probes SPI NOR in early init and loads next stage from it. --- arch/riscv/dts/k1-musepi-pro-u-boot.dtsi | 273 +++++++++++++++++++++++++++++++ board/spacemit/k1/spl.c | 24 ++- configs/spacemit_k1_defconfig | 25 ++- 3 files changed, 319 insertions(+), 3 deletions(-) diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi new file mode 100644 index 00000000000..8a9a2a09de9 --- /dev/null +++ b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2026 RISCstar Ltd. + */ + +#include <dt-bindings/clock/spacemit,k1-syscon.h> +#include "binman.dtsi" + +/ { + aliases { + console = &uart0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&syscon_mpmu { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&pll CLK_PLL1_D4>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "pll1_d4"; +}; + +&syscon_apbc { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&pll CLK_PLL1_D4>, + <&syscon_mpmu CLK_PLL1_31P5>, + <&syscon_apmu CLK_PMUA_ACLK>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "pll1_d4", "pll1_d78_31p5", "pmua_aclk"; +}; + +&uart0 { + bootph-pre-ram; +}; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; + +&i2c2 { + bootph-pre-ram; + status = "okay"; + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + resets = <&syscon_apbc RESET_TWSI2>; + + eeprom@50 { + bootph-pre-ram; + status = "okay"; + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ + pagesize = <16>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + serial-number { + }; + }; + }; +}; + +&i2c8 { + bootph-pre-ram; + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + resets = <&syscon_apbc RESET_TWSI8>; + status = "okay"; + + pmic@41 { + bootph-pre-ram; + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + status = "okay"; + + regulators { + buck1 { + bootph-pre-ram; + regulator-name = "vdd_core"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + bootph-pre-ram; + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + bootph-pre-ram; + regulator-name = "vdd_1v8_mmc"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + +&qspi { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + m25p,fast-read; + broken-flash-reset; + status = "okay"; + }; +}; + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c index 2afabc72a3f..da4169fbc8c 100644 --- a/board/spacemit/k1/spl.c +++ b/board/spacemit/k1/spl.c @@ -16,6 +16,7 @@ #include <linux/delay.h> #include <log.h> #include <power/regulator.h> +#include <spi_flash.h> #include <spl.h> #include <tlv_eeprom.h> #include "tlv_codes.h" @@ -306,6 +307,26 @@ void ddr_early_init(void) log_info("DDR is not ready\n"); } +void nor_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_SPI, 0, &dev); + if (ret) + panic("Fail to detect spi controller.\n"); + udelay(10); + ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev); + if (ret) + log_info("Fail to detect spi nor flash.\n"); + udelay(10); +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS; +} + void board_init_f(ulong dummy) { u8 i2c_buf[I2C_BUF_SIZE] = { 0 }; @@ -331,11 +352,12 @@ void board_init_f(ulong dummy) pmic_init(); ddr_early_init(); + nor_early_init(); } u32 spl_boot_device(void) { - return BOOT_DEVICE_NOR; + return BOOT_DEVICE_SPI; } void spl_board_init(void) diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index e71c079bef2..64c724c62a5 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -1,15 +1,19 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SYS_MALLOC_F_LEN=0x5000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 -CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-bananapi-f3" +CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-musepi-pro" CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 CONFIG_SPL_STACK=0xc083fb00 CONFIG_SPL_TEXT_BASE=0xc0801000 CONFIG_SPL_BSS_START_ADDR=0xc083fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0xc00000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000 CONFIG_SYS_BOOTM_LEN=0xa000000 CONFIG_SYS_LOAD_ADDR=0x200000 CONFIG_SPL_SIZE_LIMIT=0x31000 @@ -23,6 +27,8 @@ CONFIG_SPL_RISCV_MMODE=y # CONFIG_SPL_SMP is not set CONFIG_STACK_SIZE=0x100000 CONFIG_FIT=y +CONFIG_SPL_HAS_LOAD_FIT_ADDRESS=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x08000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=256 @@ -64,3 +70,18 @@ CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER_EARLY=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_FSL_QSPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_MEM=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x000a0000 +CONFIG_CMD_SPI=y +CONFIG_SPL_SPI=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y -- 2.43.0
