From: Stefan Bigler <stefan.big...@keymile.com>
The new SAMSUNG NAND Flash K9F1G08U0D require a bigger chip_delay.
The Data Transfer from Cell to Register is >= 35us. Other Vendors
and older chips normally use >= 25us. To have enough margin 40us
is selected.
Signed-off-by: Stefan Bigler <stefan.big...@keymile.com>
Signed-off-by: Holger Brunck <holger.bru...@keymile.com>
cc: Prafulla Wadaskar <prafu...@marvell.com>
cc: Stefan Roese <s...@denx.de>
---
drivers/mtd/nand/kirkwood_nand.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index 376378e..bdab5aa 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -76,7 +76,7 @@ int board_nand_init(struct nand_chip *nand)
nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = kw_nand_hwcontrol;
- nand->chip_delay = 30;
+ nand->chip_delay = 40;
nand->select_chip = kw_nand_select_chip;
return 0;
}
--
1.7.1
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