Hi Brian,
On 6/1/2026 9:13 am, Brian Sune wrote:
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CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC501 C5 to mainstream u-boot
This is a UBGA-484 based board with basic
feature. More info on [1]
[1]https://corecourse.cn/forum.php?mod=viewthread&tid=27704&highlight=AC501
Signed-off-by: Brian Sune<[email protected]>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_cyclone5_ac501soc.dts | 86 +++
.../dts/socfpga_cyclone_ac501soc-u-boot.dtsi | 44 ++
arch/arm/mach-socfpga/Kconfig | 7 +
board/corecourse/ac501soc/MAINTAINERS | 6 +
board/corecourse/ac501soc/qts/iocsr_config.h | 664 ++++++++++++++++++
board/corecourse/ac501soc/qts/pinmux_config.h | 222 ++++++
board/corecourse/ac501soc/qts/pll_config.h | 86 +++
board/corecourse/ac501soc/qts/sdram_config.h | 349 +++++++++
configs/socfpga_ac501soc_defconfig | 85 +++
include/configs/socfpga_ac501soc.h | 16 +
11 files changed, 1566 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ac501soc.dts
create mode 100644 arch/arm/dts/socfpga_cyclone_ac501soc-u-boot.dtsi
create mode 100644 board/corecourse/ac501soc/MAINTAINERS
create mode 100644 board/corecourse/ac501soc/qts/iocsr_config.h
create mode 100644 board/corecourse/ac501soc/qts/pinmux_config.h
create mode 100644 board/corecourse/ac501soc/qts/pll_config.h
create mode 100644 board/corecourse/ac501soc/qts/sdram_config.h
create mode 100644 configs/socfpga_ac501soc_defconfig
create mode 100644 include/configs/socfpga_ac501soc.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3cd762977cb..2210b44f9bf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -469,6 +469,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_cyclone5_ac501soc.dtb \
socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
new file mode 100644
index 00000000000..2c11e2088e3
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025, Brian Sune
+ *
+ * based on socfpga_cyclone5_socdk.dts
+ */
+
+#include "socfpga_cyclone5.dtsi"
+#include "socfpga-common-u-boot.dtsi"
Remove #include "socfpga-common-u-boot.dtsi" from socfpga_cyclone5_ac501soc.dts;
it’s already included via socfpga_cyclone_ac501soc-u-boot.dtsi.
+
+/ {
+ model = "CoreCourse AC501SoC";
+ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ ethernet0 = &gmac1;
+ udc0 = &usb1;
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+
+ rxd0-skew-ps = <420>;
+ rxd1-skew-ps = <420>;
+ rxd2-skew-ps = <420>;
+ rxd3-skew-ps = <420>;
+ txen-skew-ps = <0>;
+ txc-skew-ps = <1860>;
+ rxdv-skew-ps = <420>;
+ rxc-skew-ps = <1680>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
Avoid duplicating nodes between DTS and -u-boot.dtsi (e.g., GPIO bank-name).
Keep board-common settings in the DTS; U-Boot–specific settings belong
in -u-boot.dtsi
+
+&mmc0 {
+ status = "okay";
+ bootph-all;
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ bootph-all;
+};
+
+&watchdog0 {
+ status = "disabled"; +}; diff --git a/arch/arm/dts/socfpga_cyclone_ac501soc-u-boot.dtsi
b/arch/arm/dts/socfpga_cyclone_ac501soc-u-boot.dtsi new file mode
100644 index 00000000000..8d2caf69dd1 --- /dev/null +++
b/arch/arm/dts/socfpga_cyclone_ac501soc-u-boot.dtsi @@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + *
Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon
Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi"
+
+/{
+ aliases {
+ udc0 = &usb1;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&mmc {
+ bootph-all;
+};
+
+&uart0 {
+ clock-frequency = <100000000>;
+ bootph-all;
+};
+
+&uart1 {
+ clock-frequency = <100000000>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index f2e959b5662..1a0fcd64296 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -239,6 +239,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_CORECOURSE_AC501SOC
+ bool "CoreCourse AC501SoC (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
endchoice
config SYS_BOARD
@@ -263,6 +267,7 @@ config SYS_BOARD
default "sr1500" if TARGET_SOCFPGA_SR1500
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+ default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK
@@ -284,6 +289,7 @@ config SYS_VENDOR
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
config SYS_SOC
default "socfpga"
@@ -310,5 +316,6 @@ config SYS_CONFIG_NAME
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+ default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
endif
diff --git a/board/corecourse/ac501soc/MAINTAINERS
b/board/corecourse/ac501soc/MAINTAINERS
new file mode 100644
index 00000000000..e0479c9921d
--- /dev/null
+++ b/board/corecourse/ac501soc/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCFPGA BOARD
+M: Brian Sune<[email protected]>
+S: Maintained
+F: board/corecource/ac501soc/
Typo: fix path F: board/corecource/ac501soc/ → board/corecourse/ac501soc/
+F: include/configs/socfpga_ac501soc.h
+F: configs/socfpga_ac501soc_defconfig
[...]
diff --git a/include/configs/socfpga_ac501soc.h
b/include/configs/socfpga_ac501soc.h
new file mode 100644
index 00000000000..1da5c866220
--- /dev/null
+++ b/include/configs/socfpga_ac501soc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Brian Sune<[email protected]>
+ */
+#ifndef __CONFIG_CORESOURCE_AC501SOC_H__
+#define __CONFIG_CORESOURCE_AC501SOC_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */
PHYS_SDRAM_1_SIZE is legacy and not used by drivers.
Memory size should come from DT (/memory node) rather than a hard-coded
define.
Thanks.
Best regards,
Tien Fong
