When exiting a low power mode with DDR self-refresh, we can directly resume after DDR setup is done. Call the common function to resume.
Swap order of setup_qos() and spl_enable_cache(). setup_qos() is required for LPM resume but spl_enable_cache() is not required. There is no dependency between the two. Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]> --- arch/arm/mach-k3/am62ax/am62a7_init.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index c1c7d669a45f53b7528c80d44bf9b914fed1cc10..74e598d52420cd2ff59384c69d1b038a40e08cca 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -194,14 +194,24 @@ void board_init_f(ulong dummy) enable_mcu_esm_reset(); } + setup_qos(); + #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) panic("DRAM init failed: %d\n", ret); -#endif - spl_enable_cache(); - setup_qos(); + if (wkup_ctrl_is_lpm_exit()) { + u64 meta_data_addr; + + ret = wkup_r5f_am62_lpm_meta_data_addr(&meta_data_addr); + if (ret) + panic("Failed to get LPM meta data address %d\n", ret); + lpm_resume_from_ddr(meta_data_addr); + } +#endif + + spl_enable_cache(); if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && spl_boot_device() == BOOT_DEVICE_ETHERNET) { -- 2.51.0
