Hi Brian,
On 12/29/25 09:33, Brian Sune wrote:
CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC501 C5 to mainstream u-boot
This is a UBGA-484 based board with basic
feature. More info on [1]
[1] https://corecourse.cn/forum.php?mod=viewthread&tid=27704&highlight=AC501
Signed-off-by: Brian Sune <[email protected]>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/socfpga_cyclone5_ac501soc.dts | 86 +++
.../dts/socfpga_cyclone_ac501soc-u-boot.dtsi | 44 ++
arch/arm/mach-socfpga/Kconfig | 14 +
board/corecourse/ac501soc/MAINTAINERS | 6 +
board/corecourse/ac501soc/qts/iocsr_config.h | 664 ++++++++++++++++++
board/corecourse/ac501soc/qts/pinmux_config.h | 222 ++++++
board/corecourse/ac501soc/qts/pll_config.h | 86 +++
board/corecourse/ac501soc/qts/sdram_config.h | 349 +++++++++
configs/socfpga_ac501soc_defconfig | 85 +++
include/configs/socfpga_ac501soc.h | 16 +
11 files changed, 1574 insertions(+)
create mode 100644 arch/arm/dts/socfpga_cyclone5_ac501soc.dts
create mode 100644 arch/arm/dts/socfpga_cyclone_ac501soc-u-boot.dtsi
create mode 100644 board/corecourse/ac501soc/MAINTAINERS
create mode 100644 board/corecourse/ac501soc/qts/iocsr_config.h
create mode 100644 board/corecourse/ac501soc/qts/pinmux_config.h
create mode 100644 board/corecourse/ac501soc/qts/pll_config.h
create mode 100644 board/corecourse/ac501soc/qts/sdram_config.h
create mode 100644 configs/socfpga_ac501soc_defconfig
create mode 100644 include/configs/socfpga_ac501soc.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fcad6fb2fc7..40a69a13c4b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -468,6 +468,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_cyclone5_ac501soc.dtb \
+ socfpga_cyclone5_ac550soc.dtb \
You should include the build for the ac550 board in the AC550 patch.
socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc.dts b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
new file mode 100644
index 00000000000..2c11e2088e3
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025, Brian Sune
+ *
<snip>
+
+&portc {
+ bank-name = "portc";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index f2e959b5662..69af0b48348 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -239,6 +239,14 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_CORECOURSE_AC501SOC
+ bool "CoreCourse AC501SoC (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_CORECOURSE_AC550SOC
+ bool "CoreCourse AC550SoC (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
endchoice
config SYS_BOARD
@@ -263,6 +271,8 @@ config SYS_BOARD
default "sr1500" if TARGET_SOCFPGA_SR1500
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+ default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
+ default "ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK
@@ -284,6 +294,8 @@ config SYS_VENDOR
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
+ default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC550SOC
config SYS_SOC
default "socfpga"
@@ -310,5 +322,7 @@ config SYS_CONFIG_NAME
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
+ default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC
+ default "socfpga_ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC
Same comment...
Dinh
