The Rockchip TPL on some SoCs (notably RK3506) place the ATAGS region somewhere other than the default this code expects. This change allows that region to be placed somewhere different by defining ATAGS_SIZE and ATAGS_OFFSET inside a configuration header for either the SoC or the board.
Signed-off-by: Aaron Griffith <[email protected]> --- arch/arm/mach-rockchip/sdram.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 2f39928bcbda2936fb4f079bbb72fa13f80af6c0..98c02570dc4e4a8315c25a5caad5d568db10c5d8 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -38,8 +38,12 @@ struct tos_parameter_t { #ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM /* Tag size and offset */ +#ifndef ATAGS_SIZE #define ATAGS_SIZE SZ_8K +#endif +#ifndef ATAGS_OFFSET #define ATAGS_OFFSET (SZ_2M - ATAGS_SIZE) +#endif #define ATAGS_PHYS_BASE (CFG_SYS_SDRAM_BASE + ATAGS_OFFSET) #define ATAGS_PHYS_END (ATAGS_PHYS_BASE + ATAGS_SIZE) -- 2.47.3
