Enable CoreCourse Altera GEN5 Cyclone V board build support to mach-socfpga
Signed-off-by: Brian Sune <[email protected]> --- arch/arm/dts/Makefile | 2 ++ arch/arm/mach-socfpga/Kconfig | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fcad6fb2fc7..40a69a13c4b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -468,6 +468,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_cyclone5_ac501soc.dtb \ + socfpga_cyclone5_ac550soc.dtb \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f2e959b5662..69af0b48348 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -239,6 +239,14 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_CORECOURSE_AC501SOC + bool "CoreCourse AC501SoC (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + +config TARGET_SOCFPGA_CORECOURSE_AC550SOC + bool "CoreCourse AC550SoC (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + endchoice config SYS_BOARD @@ -263,6 +271,8 @@ config SYS_BOARD default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK @@ -284,6 +294,8 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_SOC default "socfpga" @@ -310,5 +322,7 @@ config SYS_CONFIG_NAME default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "socfpga_ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC endif -- 2.34.1
