On Wed, Dec 03, 2025 at 04:21:39AM -0800, Tanmay Kathpalia wrote: >- Add support for configuring the PHY DLL master control register for all > SD/eMMC timing modes (DS, HS, SDR, DDR, HS200, HS400) by extending the > PHY configuration arrays and writing the value during PHY adjustment. >- Fix tuning reliability by toggling the DLL reset before and after > updating the PHY_DLL_SLAVE_CTRL_REG_ADDR register. > >Signed-off-by: Tanmay Kathpalia <[email protected]> >Reviewed-by: Balsundar Ponnusamy <[email protected]>
Acked-by: Peng Fan <[email protected]>
