On Sat, Nov 29, 2025 at 09:56:44AM +0530, Kumar, Udit wrote: > > On 11/29/2025 12:54 AM, Ernest Van Hoecke wrote: > > On Wed, Nov 26, 2025 at 06:34:15PM +0530, Kumar, Udit wrote: > > > Thanks Ernest for reviving this patch , > > > > > > Changes in arch/arm/mach-k3/common.c seems good to me. > > > > > > but common/spl/spl.c can not pushed in generic way, I can think of few > > > platforms running SPL w/o caches on. > > > > > Hi Udit, > > > > Thanks for your prompt reply and input. I have now tested this patch but > > with the enable_caches in common/spl/spl.c dropped, and everything looks > > great to me. I will continue running the tests over the weekend, but can > > confirm that this change seems unnecessary to fix the issue we saw with > > sporadic boot failures. > > Thanks again Ernest, > > Ideally, I prefer to revert commit sha 52a86e69e20. > > Adding more TI folks for any objection on reverting sha 52a86e69e20 > > > > > A v2 that only touches mach-k3/common.c would be suitable. If you > > prefer, I have a patch ready that we can send. I don't believe much > > Unfortunately, only change in mach-k3/common.c will not be enough to fix the > issue. > > we need to clean-caches at board_init_r stage, and which is common code. >
Thanks Kumar, I'm assuming the issue is that there are still a number of instructions executing after the SPL relocation until we finally disable icache in spl_board_prepare_for_boot? With 50k boots over the weekend I can confirm that, for the AM69A with our test setup here on a TI AM69 SDK, the issue did not occur again. I agree that we might need to find a better place to invalidate the caches if necessary, but commit 52a86e69e20 was necessary to not have a 1.3 second delay between the A53 SPL and A53 U-Boot on the AM62 as reported on E2E. [1] [1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1217839/am625-boot-time-between-a53-spl-and-a53-u-boot Thanks for your help here. Kind regards, Ernest
