Hi, On Thu Jul 31, 2025 at 9:59 AM CEST, Chintan Vankar wrote: > Update dev-data and clk-data to include CPSW device which is required to > enable Ethernet boot. >
This breaks eMMC boot on our board: U-Boot SPL 2026.01-rc2-00054-g32334645579c (Nov 21 2025 - 15:49:13 +0100) SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.3--v11.01.03 (Fancy Rat)') SPL initial stack usage: 17048 bytes ti_power_domain_of_xlate: invalid dev-id: 57 ti_power_domain_of_xlate: invalid dev-id: 57 Trying to boot from eMMC (boot0) ti_power_domain_of_xlate: invalid dev-id: 57 ti_power_domain_of_xlate: invalid dev-id: 57 spl: could not initialize mmc. error: -2 Error: -2 SPL: Unsupported Boot Device! SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Not sure how this file was autogenerated but it removes ID 57.. see more below. Reverting this patch will make (at least) the r5 SPL work again. There seems to be more issues with the u-boot proper, but I haven't investigated that yet. > Signed-off-by: Chintan Vankar <[email protected]> > --- > > Link to v3: > https://lore.kernel.org/u-boot/[email protected]/ > > Changes from v3 to v4: > - No changes. > > arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++------ > arch/arm/mach-k3/r5/j722s/dev-data.c | 34 +++++++++---------- > 2 files changed, 56 insertions(+), 28 deletions(-) > > diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c > b/arch/arm/mach-k3/r5/j722s/clk-data.c > index b4f27af333d..238d57d0aa0 100644 > --- a/arch/arm/mach-k3/r5/j722s/clk-data.c > +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c > @@ -5,7 +5,7 @@ > * This file is auto generated. Please do not hand edit and report any issues > * to Bryan Brattlof <[email protected]>. > * > - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ > + * Copyright (C) 2020-2025 Texas Instruments Incorporated - > https://www.ti.com/ > */ > > #include <linux/clk-provider.h> > @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = { > "hsdiv4_16fft_main_2_hsdivout1_clk", > }; > > -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { > - "postdiv4_16ff_main_0_hsdivout5_clk", > - "hsdiv4_16fft_main_2_hsdivout2_clk", > +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { > + "postdiv4_16ff_main_2_hsdivout5_clk", > + "postdiv4_16ff_main_0_hsdivout6_clk", > + "board_0_cp_gemac_cpts0_rft_clk_out", > + NULL, > + "board_0_mcu_ext_refclk0_out", > + "board_0_ext_refclk1_out", > + NULL, > + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", > }; > > static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { > @@ -94,8 +100,8 @@ static const char * const > main_timerclkn_sel_out0_parents[] = { > "board_0_cp_gemac_cpts0_rft_clk_out", > "hsdiv4_16fft_main_1_hsdivout3_clk", > "postdiv4_16ff_main_2_hsdivout6_clk", > - NULL, > - NULL, > + "cpsw_3guss_am67_main_0_cpts_genf0", > + "cpsw_3guss_am67_main_0_cpts_genf1", > NULL, > NULL, > NULL, > @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = { > CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), > CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), > CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), > + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), > + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), > CLK_FIXED_RATE("board_0_tck_out", 0, 0), > + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), > + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), > + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), > CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), > CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), > CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), > @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = { > CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", > sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), > CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", > "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), > CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, > 1, 0), > - CLK_MUX("main_emmcsd0_refclk_sel_out0", > main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), > + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", > main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), > CLK_MUX("main_emmcsd1_refclk_sel_out0", > main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), > CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, > 0x43008030, 0, 3, 0), > CLK_MUX("main_ospi_ref_clk_sel_out0", > main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), > @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = { > }; > > static const struct dev_clk soc_dev_clk_data[] = { > + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), > + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), > + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), > + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), > + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), > + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), > + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), > + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), > + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), > DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), > DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), > DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), > @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = { > DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), > DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), > DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), > - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), > - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), > - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), > + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), > + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), > DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), > DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), > DEV_CLK(58, 2, "board_0_mmc1_clk_out"), > @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = { > DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), > DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), > DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), > + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), > DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), > DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), > DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), > diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c > b/arch/arm/mach-k3/r5/j722s/dev-data.c > index 59176c98999..d6832266884 100644 > --- a/arch/arm/mach-k3/r5/j722s/dev-data.c > +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c > @@ -5,7 +5,7 @@ > * This file is auto generated. Please do not hand edit and report any issues > * to Bryan Brattlof <[email protected]>. > * > - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ > + * Copyright (C) 2020-2025 Texas Instruments Incorporated - > https://www.ti.com/ > */ > > #include "k3-dev.h" > @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = { > > static struct ti_lpsc soc_lpsc_list[] = { > [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), > - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[5]), > - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[5]), > - [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[7]), > - [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[7]), > - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[7]), > - [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[7]), > - [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[7]), > - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], > &soc_lpsc_list[7]), > + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[4]), > + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[4]), > + [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[6]), > + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[6]), > + [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[6]), > + [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[6]), > + [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], > &soc_lpsc_list[6]), > + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], > &soc_lpsc_list[6]), > [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], > &soc_lpsc_list[8]), > - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], > &soc_lpsc_list[7]), > + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], > &soc_lpsc_list[6]), > [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], > &soc_lpsc_list[10]), > [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], > &soc_lpsc_list[11]), > }; > @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = { > PSC_DEV(61, &soc_lpsc_list[0]), > PSC_DEV(178, &soc_lpsc_list[1]), > PSC_DEV(179, &soc_lpsc_list[2]), > - PSC_DEV(57, &soc_lpsc_list[3]), This seems to be relevant. -michael > - PSC_DEV(58, &soc_lpsc_list[4]), > - PSC_DEV(161, &soc_lpsc_list[5]), > - PSC_DEV(75, &soc_lpsc_list[6]), > - PSC_DEV(36, &soc_lpsc_list[7]), > - PSC_DEV(102, &soc_lpsc_list[7]), > - PSC_DEV(146, &soc_lpsc_list[7]), > + PSC_DEV(58, &soc_lpsc_list[3]), > + PSC_DEV(161, &soc_lpsc_list[4]), > + PSC_DEV(75, &soc_lpsc_list[5]), > + PSC_DEV(36, &soc_lpsc_list[6]), > + PSC_DEV(102, &soc_lpsc_list[6]), > + PSC_DEV(146, &soc_lpsc_list[6]), > + PSC_DEV(13, &soc_lpsc_list[7]), > PSC_DEV(166, &soc_lpsc_list[8]), > PSC_DEV(135, &soc_lpsc_list[9]), > PSC_DEV(170, &soc_lpsc_list[10]),
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