From: Takahiro Kuwano <[email protected]> In parallel mode, status register value of two chips need to be read and evaluated. Currenlty spi-nor-core takes care for that by reading two bytes and performing logical AND of two bytes for read_sr() and read_fsr(), assuming the controller performs byte interleaving in parallel mode, but it depends on controller specification.
Controller driver should take care for parallel mode to read status registers. Signed-off-by: Takahiro Kuwano <[email protected]> --- drivers/spi/zynq_qspi.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 67005a3b8df..3d9fc11314f 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -753,6 +753,17 @@ static bool update_stripe(const struct spi_mem_op *op) return true; } +static bool zynq_qspi_is_read_status(const struct spi_mem_op *op) +{ + switch (op->cmd.opcode) { + case SPINOR_OP_RDSR: + case SPINOR_OP_RDFSR: + return true; + } + + return false; +} + static int zynq_qspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { @@ -762,6 +773,7 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, unsigned int flag = 0; const u8 *tx_buf = NULL; u8 *rx_buf = NULL; + u8 sr_buf[2]; if (op->data.nbytes) { if (op->data.dir == SPI_MEM_DATA_IN) @@ -805,10 +817,20 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, /* 2nd transfer: rx or tx data path */ if (tx_buf || rx_buf) { - ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf, - rx_buf, flag | SPI_XFER_END); + op_len = op->data.nbytes; + + if (priv->is_parallel && zynq_qspi_is_read_status(op)) { + rx_buf = sr_buf; + op_len = 2; + } + + ret = zynq_qspi_xfer(slave->dev, op_len * 8, tx_buf, rx_buf, + flag | SPI_XFER_END); if (ret) return ret; + + if (priv->is_parallel && zynq_qspi_is_read_status(op)) + *(u8 *)op->data.buf.in = sr_buf[0] & sr_buf[1]; } spi_release_bus(slave); -- 2.34.1
