Minor clock adjustment for new A733 MMC controller, the SMHC0_CLK_REG start at offset 0x400, and with step size of 0x10.
Signed-off-by: Yixun Lan <[email protected]> --- drivers/mmc/sunxi_mmc.c | 32 ++++++++++++++++++++++++++------ drivers/mmc/sunxi_mmc.h | 3 ++- 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index e28c81afffe..75acfb25e86 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -61,6 +61,7 @@ static bool sunxi_mmc_can_calibrate(void) IS_ENABLED(CONFIG_MACH_SUN50I_H5) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || + IS_ENABLED(CONFIG_MACH_SUN60I_A733) || IS_ENABLED(CONFIG_MACH_SUN8I_R40); } @@ -112,6 +113,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (priv->mmc_no == 2) pll_hz *= 2; } + + if (IS_ENABLED(CONFIG_MACH_SUN60I_A733)) + pll_hz /= 3; } div = pll_hz / hz; @@ -167,7 +171,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) } /* The A523 has a second divider, not a shift. */ - if (IS_ENABLED(CONFIG_MACH_SUN55I_A523)) + if (IS_ENABLED(CONFIG_MACH_SUN55I_A523) || + IS_ENABLED(CONFIG_MACH_SUN60I_A733)) n = (1U << n) - 1; writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | @@ -219,7 +224,8 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr); -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || \ + defined(CONFIG_SUNXI_GEN_NCAT2) || defined(CONFIG_MACH_SUN60I_A733) /* A64 supports calibration of delays on MMC controller and we * have to set delay of zero before starting calibration. * Allwinner BSP driver sets a delay only in the case of @@ -472,7 +478,9 @@ static void sunxi_mmc_reset(void *regs) writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL); udelay(1000); - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) { + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || + IS_ENABLED(CONFIG_MACH_SUN60I_A733)) { /* Reset card */ writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST); udelay(10); @@ -591,7 +599,8 @@ struct mmc *sunxi_mmc_init(int sdc_no) /* config ahb clock */ debug("init mmc %d clock and io\n", sdc_no); -#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) +#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) && \ + !defined(CONFIG_MACH_SUN60I_A733) setbits_le32(ccm + CCU_AHB_GATE0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -661,17 +670,28 @@ static const struct dm_mmc_ops sunxi_mmc_ops = { .get_cd = sunxi_mmc_getcd, }; -static unsigned get_mclk_offset(void) +static unsigned int get_mclk_offset(void) { if (IS_ENABLED(CONFIG_MACH_SUN9I_A80)) return 0x410; + if (IS_ENABLED(CONFIG_MACH_SUN60I_A733)) + return 0xd00; + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) return 0x830; return 0x88; }; +static unsigned int get_mclk_size(void) +{ + if (IS_ENABLED(CONFIG_MACH_SUN60I_A733)) + return 0x10; + + return 0x4; +}; + static int sunxi_mmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -707,7 +727,7 @@ static int sunxi_mmc_probe(struct udevice *dev) ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node); priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; - priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4; + priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * get_mclk_size(); ret = clk_get_by_name(dev, "ahb", &gate_clk); if (!ret) diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h index 71865160319..a5caca15ba5 100644 --- a/drivers/mmc/sunxi_mmc.h +++ b/drivers/mmc/sunxi_mmc.h @@ -47,7 +47,8 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res2[26]; -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || \ + defined(CONFIG_SUNXI_GEN_NCAT2) || defined(CONFIG_MACH_SUN60I_A733) u32 thldc; /* 0x100 Threshold control */ u32 res3[16]; u32 samp_dl; -- 2.51.2
