Setup correct UART base address for A733 SoC. According to Allwinner's board design, A733 SoC use the UART0 port for serial console, so config PB9-10 pins to setup pinmux.
Signed-off-by: Yixun Lan <[email protected]> --- arch/arm/include/asm/arch-sunxi/serial.h | 2 +- arch/arm/mach-sunxi/board.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h index 9386287b65e..57b62ac8c7e 100644 --- a/arch/arm/include/asm/arch-sunxi/serial.h +++ b/arch/arm/include/asm/arch-sunxi/serial.h @@ -17,7 +17,7 @@ #elif defined(CONFIG_MACH_SUNIV) #define SUNXI_UART0_BASE 0x01c25000 #define SUNXI_R_UART_BASE 0 -#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#elif defined(CONFIG_SUNXI_GEN_NCAT2) || defined(CONFIG_MACH_SUN60I_A733) #define SUNXI_UART0_BASE 0x02500000 #define SUNXI_R_UART_BASE 0 // 0x07080000 (?> #else diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 432b1c10f92..72c9fc413cb 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -141,7 +141,8 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_H616_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN50I_H616_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN55I_A523) +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN55I_A523) || \ + defined(CONFIG_MACH_SUN60I_A733)) sunxi_gpio_set_cfgpin(SUNXI_GPB(9), 2); sunxi_gpio_set_cfgpin(SUNXI_GPB(10), 2); sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); -- 2.51.2
