> a) reset > b) clock manager Short investigation and test shown that the watchdog is the root cause. (Not proved by code review just test run proposed)
This is not 100% sure but what is observed from the board boot via terminal repetitively stop at SDRAM calibration. Doing a cross-check from Altera SoCFPGA trunk shows a Kconfig different. After modified the Kconfig and select WDT and required driver. The SDRAM calibration fail no longer triggered. Power cycling and soft reset shows no issue. Patch will be applied to fix this issue. ``` U-Boot 2026.01-rc2-00033-gbee3c63434db-dirty (Nov 15 2025 - 19:17:31 +0800) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A5 or SX/C5 or ST/D5, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) DRAM: 2 GiB Core: 33 devices, 18 uclasses, devicetree: separate WDT: Started watchdog@ffd02000 with servicing every 1000ms (10s timeout) MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... Reading from MMC(0)... OK In: serial Out: serial Err: serial Model: Altera SOCFPGA Cyclone V SoC Development Kit Net: eth0: ethernet@ff702000 Hit any key to stop autoboot: 3 ``` Brian
