On Mon, Nov 10, 2025 at 03:11:40PM +0530, Hrushikesh Salunke wrote: > To enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled > and configured at r5 stage. Add the required clk-data and dev-data > for SERDES0 and PCIE1. > > Signed-off-by: Hrushikesh Salunke <[email protected]> > --- > arch/arm/mach-k3/r5/j784s4/clk-data.c | 211 ++++++++++++++++++++++++-- > arch/arm/mach-k3/r5/j784s4/dev-data.c | 45 +++--- > 2 files changed, 227 insertions(+), 29 deletions(-) > > diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c > b/arch/arm/mach-k3/r5/j784s4/clk-data.c > index 24780eb6562..7ea67ce38f5 100644 > --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c > +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c > @@ -1,11 +1,11 @@ > -// SPDX-License-Identifier: GPL-2.0-or-later > +// SPDX-License-Identifier: GPL-2.0+
This is wrong, "GPL-2.0-or-later" is the newer SPDX tag. Please go fix the tooling if needed, thanks. -- Tom
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