Add this option to allow boards to override the default read-to-write
turnaround time for better performance.
Signed-off-by: York Sun <york...@freescale.com>
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++
arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 +++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 02d069c..3824aad 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -267,6 +267,9 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
tmrd_mclk = 2;
#endif
+ if (popts->trwt_override)
+ trwt_mclk = popts->trwt;
+
ddr->timing_cfg_0 = (0
| ((trwt_mclk & 0x3) << 30) /* RWT */
| ((twrt_mclk & 0x3) << 28) /* WRT */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h
b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 1778cc5..bc063ea 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -271,6 +271,9 @@ typedef struct memctl_options_s {
unsigned int rcw_2;
/* control register 1 */
unsigned int ddr_cdr1;
+
+ unsigned int trwt_override;
+ unsigned int trwt; /* read-to-write turnaround */
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
--
1.7.0.4
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